tag: IBM

Betting On 3D
By Ed Sperling - 26 Aug, 2010 - Comments: 0

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 23 Jul, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpt... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 16 Jul, 2010 - Comments: 0

Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that convers... » read more

EUV Focus Shifts To Affordability
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By David Lammers Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, ... » read more

Keeping Models In Sync
By Ed Sperling - 08 Jul, 2010 - Comments: 0

By Ed Sperling Models and higher levels of abstraction have been hailed as the best choice for developing SoCs at advanced process nodes, but at 28nm and beyond even that approach is showing signs of stress. The number of models needed for a complex SoC has been growing at each new process node, which makes it much more difficult to keep them updated and in sync as the design progresses down t... » read more

Experts At The Table: The Power Problem
By Ed Sperling - 08 Jul, 2010 - Comments: 0

Low-Power Engineering sat down to discuss a broad swath of power issues with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that conversa... » read more

Pricey Processes For Low Power
By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Pallab Chatterjee Recently Samsung gave an update on the status and availability of its advanced 32/28nm process technology for use in foundry. The process is targeted for shipping designs to customers at the end of this year, with a road map that continues through the 22/20nm nodes and down to 15nm. What was particularly interesting were several key innovations that have made this all p... » read more

It’s All About Power
By Ann Mutschler - 08 Apr, 2010 - Comments: 0

In my last entry regarding IBM’s claim for new x86 technology for the datacenter, I mentioned I was trying to get an answer from IBM regarding details on the “silicon innovation” it used. That quest is ongoing, and I hope to find some actual technology, and not just marketing mumbo-jumbo at the heart of it. Keep checking back, I will give my report here. Just a few weeks after Big Blue... » read more

Grappling With Graphene
By Brian Fuller - 11 Mar, 2010 - Comments: 0

By Brian Fuller Silicon CMOS is a tough act to follow. The workhorse building block for the world’s electronics has been delivering for system designers for a half century. Despite hand-wringing over its apparent scalability limits, it shows only vague signs of slowing down. For nearly as many years, it seems, the next great material or alternative to silicon CMOS has popped into the indu... » read more

The Long And Painful Path To Power Optimization
By Ed Sperling - 11 Mar, 2010 - Comments: 0

By Ed Sperling Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago. Perhaps even more astounding is the price drop on these devices. A basic cell ... » read more

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