Making Too Much Noise


By Ed Sperling For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change. Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signal... » read more

Anatomy Of A (Better) Gaming Platform


By Pallab Chatterjee Microsoft’s third-generation Xbox360 engine uses a 45nm silicon on insulator (SOI) process—and a new architecture. The original design was on 90nm and then migrated to 65nm. In both of these cases the fundamental architecture of the system remained the same—a CPU (central processing unit) chip, a GPU (graphics processing unit) chip, and memory management chip for ... » read more

Moving To Open-Source Software


By Ann Steffora Mutschler With the typical cost of software accounting for 40% to 60% of an SoC, semiconductor OEMs are under more pressure than ever to meet margins. As a result, they are drawing on their ecosystem partners to provide a more complete foundation including hardware, software, FPGA prototypes, verification IP and virtual models, as well as an increasing demand for open source so... » read more

A New Reference For Low-Power Processors


By Pallab Chattejee Just how much power can you squeeze out of a processor without destroying performance? Ask IBM. The company introduced a new methodology for power and energy management on its multicore processor chips. The new PowerPC chip, the Power 7, has eight main processor cores each with its own L2 and L3 cache and two central memory controllers. The architecture for the design is... » read more

Changes In The Ecosystem


By Ed Sperling For the better part of two decades, semiconductor companies have been talking about ecosystems mostly for marketing and economic reasons. They’re now talking thinking about ecosystems for complex technology reasons that involve integrated models for power, transactions and manufacturability. In the late 1990s, IBM began assembling its own loose ecosystem as a way of shieldi... » read more

The Shape Of Things To Come


By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

Betting On 3D


The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Experts At The Table: The Power Problem


By Ed Sperling Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpt... » read more

Experts At The Table: The Power Problem


Low-Power Engineering sat down to discuss the issues in low-power design with Vic Kulkarni, general manager and senior vice president of the RTL business unit, Apache Design Solutions; Pete Hardee, solutions marketing manager at Cadence; Bernard Murphy, chief technology officer at Atrenta, and Bhavna Agrawal, manager of circuit design automation at IBM. What follows are excerpts of that convers... » read more

EUV Focus Shifts To Affordability


By David Lammers Over the past year, key technologists in the semiconductor industry have come around to believing that EUV lithography will be available for critical mask layers in the next three to five years. What is still up for debate is whether EUV will be cost-effective for low-power consumer SoCs. To penetrate that cost-sensitive market, EUV must overcoming hurdles presented by masks, ... » read more

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