The Shape Of Things To Come

Next-generation transistors will be different, but industry is divided over whether to use planar ETSOI or finFETs


By David Lammers
Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations.

“This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech. “Many companies are assessing the ETSOI path as a way to build on their history of planar devices. But other companies are considering non-planar devices, perhaps because they see a longer scaling path. The next year will be a period of intense evaluation and development.”

Thomas Hoffmann, the front end of the line program manager at Imec, said many of the fabless companies that belong to Imec’s Insite program—which allows the large fabless IC vendors to gain early understanding about technology trends—are now asking for information about finFETs. During the first year of the Insite program, the main topic of interest was high-k/metal gate technology.

“Today, there are a lot of questions about finFETs, and not so many about high-k, which they may have already tackled,” Hoffmann said. “Many of them expect one of the major foundries to adopt finFETs.”

At the Imec technology forum, TSMC senior vice president of technology S.Y. Chiang confirmed that finFETs were on the foundry’s roadmap. “We evaluated the device physics and decided that we cannot extend planar devices that far. So we will use finFETs at the 14nm node.”

Before then, Intel may lead the way into vertical transistors, using its tri-gate design as early as the 22nm node. With its history of pushing bulk silicon technology, Intel may adopt vertical devices on bulk silicon wafers rather than switching to the more-expensive SOI wafers. University of Florida Professor Scott Thompson, who earlier worked at Intel, is among those predicting an early switch by Intel to the vertical dimension at the 22 nm generation. Others believe Intel will figure out how to extend planar bulk technology at the 22nm node.

Though it is still evaluating finFETs, analysts including Gartner Inc.’s Dean Freeman expect the Fishkill Alliance to switch to ETSOI at the 22nm node, taking advantage of the ability to fully deplete carriers from the thin channel. IBM has worked closely with its primary SOI wafer supplier, Soitec (Bernin, France), to create a volume supply of extra-thin SOI wafers with a top silicon thickness of 12nm, plus or minus .5 nm. Maintaining uniformity of the top silicon layer is critical to controlling the threshold voltage in ETSOI technology.

Imec’s Hoffman said at the 22nm generation, about 75% of the process steps used to create planar transistors are also common to a finFET process flow. “When it comes down to the 22nm node, I wouldn’t be surprised if IBM goes to a fully depleted SOI technology. In the first order, companies have to figure out how to scale the gate length, but ultimately they will do it in order to scale the supply voltage.”

Yannick Le Tiec, a researcher at Leti (Grenoble, France) now working at the Fishkill Alliance, said the undoped channel in ETSOI technology removes the problem of dopants moving around during the high-temperature steps. Also, ETSOI improves control of the gate. “We can use the buried oxide layer of SOI and create a back bias at the ground plane. That is an option that bulk technologies don’t have,” Le Tiec said.

Fig. 1:Fully depleted SOI devices with a gate length of 40 nm and a thin (10 nm) buried oxide. (Source: STMicroelectronics, Leti, and Soitec presentation at 2010 Symposium on VLSI Technology)

Fig. 1:Fully depleted SOI devices with a gate length of 40 nm and a thin (10 nm) buried oxide. (Source: STMicroelectronics, Leti, and Soitec presentation at 2010 Symposium on VLSI Technology)

With strain techniques and high-k/metal gates pushed close to their limits, leading-edge IC vendors have to do something new to keep power consumption under control, said Jan Rabaey, head of the Gigascale Systems Research Center at the University of California at Berkeley. The undoped channel in ETSOI “gets around the key problem for leading-edge devices, which is the random variability of the dopants.” Also, by putting a fourth terminal beneath the oxide, Rabaey said ETSOI transistors can improve the ability to fully turn off the transistors.

“Intel is very committed to finFETs, and TSMC also is talking about finFETs at the 15nm node. But ETSOI is a technology that may be more amenable to rapid deployment,” Rabaey said. FinFETs would require a “total redesign of any company’s hard IP,” he said. With vertical transistors, the design rules governing spacing, proximity, and density all will change. And vertical transistors require innovations in manufacturing as well, including lithography and CMP.

Caption for FinFETSRAM: At the 2010 Symposium on VLSI Technology, IBM Research and other members of the Fishkill Alliance presented a finFET SRAM cell measuring 0.094 μm2

Fig. 2: At the 2010 Symposium on VLSI Technology, IBM Research and other members of the Fishkill Alliance presented a finFET SRAM cell measuring 0.094 μm2

At 22nm and beyond, the design community is likely to see the major foundries go in different directions. TSMC may support a bulk 22nm flow, while GlobalFoundries, Samsung, IBM, and other members of the Fishkill Alliance may commit to a planar ETSOI process. If TSMC follows through on its commitment to finFETs at the 15nm generation, the EDA, IP, and fabless semiconductor companies may confront another divide, with TSMC adopting vertical transistors while GlobalFoundries and others remain planar. At that point, Rabaey said foundries will need to get much more involved with design, and fabless companies will “have to know a lot more about the process.”

Gap-fill challenges
The shift to vertical transistors will require new manufacturing techniques, said Randhir Thakur, general manager of the Silicon Systems Group at Applied Materials. Applied unveiled a flowable CVD (FCVD) tool on Aug. 24 that is aimed at finFETs and vertical memory devices where conventional CVD dielectrics and spin-on dielectrics (SOD) both run out of gas. Electrical isolation of the vertical transistors requires filling the isolation trenches with dielectrics from the bottom up, rather than from the sides.

“FinFETs raise the complexity beyond what spin-on dielectrics can handle. Those chemistries also have a lot of carbon, which creates fixed charges,” Thakur said in announcing Applied’s “Producer Eterna” flowable CVD tool.

The Eterna system includes a proprietary precursor, a carbon-free chemistry that can fill 10nm openings with very high (30:1) aspect ratios. “If carbon is introduced, that causes the threshold voltage to shift and creates leakage,” said Bill McClintock, general manager of Applied’s dielectric systems and chemical mechanical planarization products. Also, finFET manufacturing requires relatively low processing temperatures. “Going forward, these new device architectures involve filling gaps which are not doable with the current systems on the market,” he said.