tag: IP

Rethinking Memory
By Ed Sperling - 16 Dec, 2015 - Comments: 3

Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

New Approaches To Low Power Design
By Ann Mutschler - 14 Dec, 2015 - Comments: 1

While Moore's Law continues to drive feature size reduction and complexity, a whole separate part of the industry is growing up around vertical markets in the IoT. While these two worlds may be different in many respects, they share one thing in common—low power design is critical to success. How engineering teams minimize power in each of these markets, and even within the same market, ca... » read more

What Goes Wrong With IP
By Ed Sperling - 10 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

2016 And Beyond
By Krishna Balachandran - 10 Dec, 2015 - Comments: 0

Greek mythology and Roman history are replete with soothsayers, some of whom got it right and others wrong. Cassandra was cursed that her predictions wouldn’t be believed, even though she predicted the Trojan horse. Caesar’s soothsayer predicted the demise of Julius Caesar during the Ides of March, which Caesar himself was skeptical about, but indeed he was murdered before the Ides passed. ... » read more

Safety in SoCs
By Synopsys - 09 Dec, 2015 - Comments: 0

Today’s system-on-chip (SoC) designs are becoming more complex, increasing the pressure on verification and design teams to deliver fully functional designs. Recent studies have shown that over 50% of the development time on a complex IC is now being spent on verification, revealing the severity of the problem project teams are facing. As more SoC designs are used in electronic systems deploy... » read more

New IP Risks
By Ernest Worthman - 09 Dec, 2015 - Comments: 0

The world is being flooded with Internet-enabled devices, from smart toothbrushes to smart appliances to smart aircraft, and everything in between. Some of this is expected to be connected to the Internet, and some has been for quite some time. But devices such as smart toothbrushes and smart socks pose a whole new challenge. The issue is that even low-end chips need some sort of IP, but if ... » read more

Power, Standards And The IoT
By Ed Sperling - 08 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss power, standards and the IoT with Jerry Frenkil, director of open standards at [getentity id="22055" comment="Si2"]; Frank Schirrmeister, group director of product marketing of the System Development Suite at [getentity id="22032" e_name="Cadence"]; Randy Smith, vice president of marketing at [getentity id="22605" e_name="Sonics"]; and Vojin Zivojno... » read more

Defining Sufficient Coverage
By Brian Bailey - 07 Dec, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

The Silicon Foundry Market Is Alive And Well
By Rich Wawrzyniak - 19 Nov, 2015 - Comments: 0

I attended the ARM TechCon conference in Santa Clara last week and met with the GlobalFoundries team to discuss their new 14nm finFET technology. GlobalFoundries’ 14LPP technology offering was qualified in the third quarter of 2015 and is on track for volume production in 2016. FX-14 design kits are available to customers now.  This announcement was the culmination of an extensive body of... » read more

Tech Talk: 14nm And Stacked Die
By Ed Sperling - 11 Nov, 2015 - Comments: 0

Aashish Malhotra, marketing director for the ASIC Business Unit at GlobalFoundries, talks about 14nm process technology, the IP ecosystem, and why that technology node will be used as a platform for 2.5D and 3D stacked die across a wide range of markets including the Internet of Everything. [youtube vid=ukTRuedB7ZU] » read more

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