The Next Incarnation Of EDA

By Brian Bailey - 25 Aug, 2022 - Comments: 0

The EDA industry has incrementally addressed issues as they arise in the design of electronic systems, but is there about to be a disruption? Academia is certainly seeing that as a possibility, but not all of them see it happening for the same reason. The academic community questioned the future of EDA at the recent Design Automation Conference. Rather than EDA as we know it going away, they... » read more

Technical Paper Round-Up: Aug 23

By Linda Christensen - 23 Aug, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Chipmakers Model AI For Radio Access Networks

By Martha DeGrasse - 22 Aug, 2022 - Comments: 0

The chips that power and connect smartphones are now foundational to a disparate portfolio of daily tasks we take for granted, from accessing the internet to snapping a photo or asking Siri or Google if rain is in the forecast. Most people don’t think twice about the conflicting demands these tasks can place on semiconductors, but for engineers at leading chip manufacturers, this balancing ac... » read more

DNN-Opt, A Novel Deep Neural Network (DNN) Based Black-Box Optimization Framework For Analog Sizing

By Technical Paper Link - 19 Aug, 2022 - Comments: 0

This technical paper titled "DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks" is co-authored from researchers at The University of Texas at Austin, Intel, University of Glasgow. The paper was a best paper candidate at DAC 2021. "In this paper, we present DNN-Opt, a novel Deep Neural Network (DNN) based black-box optimization framework for analog sizi... » read more

Week In Review: Manufacturing, Test

By Karen Heyman - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department issued export controls on key technologies, including gallium oxide (Ga2O3) and diamond substrates, which are used at high voltages and temperatures, as well as EDA tools specifically developed for GAA FETs. It's not clear how this will impact EDA companies, because many of the tools that will be used for designing for GAA FETs already are in use today for finFETs. ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 19 Aug, 2022 - Comments: 0

The U.S. Commerce Department's Bureau of Industry and Security (BIS) issued new export controls on EDA software aimed at designing gate-all-around FETs, which manufacturers plan to implement starting at 3nm (Samsung) and 2nm (Intel and TSMC). Specifically, the ruling controls export of software that is specially designed for implementing RTL to GDSII (or an equivalent standard) for GAA FET desi... » read more

Week in Review: Auto, Security, Pervasive Computing

By Marie C. Baca - 19 Aug, 2022 - Comments: 0

Automotive and Mobility Lyft launched a new robotaxi service that operates on and around the Las Vegas Strip using the electric Ioniq 5 vehicle from Motional. Similar services by other companies are currently in use in a handful of other U.S. cities, including San Francisco and Phoenix. The new Lyft service currently requires the presence of safety drivers, though Lyft and Motional say it will... » read more

Implementing Cryptographic Algorithms for the RISC-V Instruction Set Architecture in Two Cases

By Technical Paper Link - 18 Aug, 2022 - Comments: 0

This new technical paper titled "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms" was published by researchers at Intel, North Arizona University and Google, with partial funding from U.S. Air Force Research Laboratory. Abstract "The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient i... » read more

Big Changes In Architectures, Transistors, Materials

By Ed Sperling - 18 Aug, 2022 - Comments: 0

Chipmakers are gearing up for fundamental changes in architectures, materials, and basic structures like transistors and interconnects. The net result will be more process steps, increased complexity for each of those steps, and rising costs across the board. At the leading-edge, finFETs will run out of steam somewhere after the 3nm (30 angstrom) node. The three foundries still working at th... » read more

Formal Verification Methodology For Detecting Security-Critical Bugs in HW & in the HW/Firmware Interface of SoCs (Award Winner)

By Technical Paper Link - 17 Aug, 2022 - Comments: 0

A new technical paper titled "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level" was this year's first place winner of Intel's Hardware Security Academic Award program. The approach utilizes UPEC (Unique Program Execution Checking) to identify functional design bugs causing confidentiality violations, covering both the processor and its peripherals. ... » read more

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Knowledge Centers
Entities, people and technologies explored

Intel Vs. Samsung Vs. TSMC

Foundry competition heats up in three dimensions and with novel technologies as planar scaling benefits diminish.

by Ed Sperling

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Chip Industry Week In Review

Softbank's acquisition; advanced packaging funding; glass substrates; engineered copper wire; semi equipment set new record; HBM4; AI chips rake in funding; X-ray inspection; apprenticeships.

by The SE Staff

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: Intel