Supply Chain Adjusts To Design At The System Level

By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler System-level design is impacting the supply chain at many levels. Software suppliers, IP providers, semiconductor companies, system integrators and OEMs are challenged to work ever more closely together and find a new balance of power for who controls what in the content of an SoC. “We see more and more the design chain driving how our tools work together,” Fra... » read more

Redefining Performance In Mobile Devices

By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler While mobile product trends can be reliably unpredictable, devices are definitely moving towards supporting more software-based browsers, plug-ins for browsers, and downloaded codecs to go to browsers. This results in coming up with a best guess for performance targets. Throw power tradeoffs into the mix and things really start to get interesting. In terms of defin... » read more

From Multicore To Many-Core

By Ed Sperling - 23 Sep, 2010 - Comments: 0

By Ed Sperling Future SoCs will move from multiple cores—typically two to four in a high-power processor—to dozens of cores. But answers are only beginning to emerge as to where and how those cores will be deployed and how they will be accessed. Just as Moore’s Law forced a move to multicore architectures inside a single processor because of leakage at higher frequencies, it will begi... » read more

Storm Before The Calm

By Ed Sperling - 17 Sep, 2010 - Comments: 0

The announcements out of ARM and Intel over the past couple week—and presumably from rivals AMD, MIPS and even Nvidia in coming weeks—are more than just a struggle for one-upmanship. The goal is much more far-reaching and the stakes are significantly higher than who has the fastest processor or core or even the lowest-power version. In the past year there has been a massive push to expan... » read more

The Growing Software Challenge: From Stacks To SMP

By Ann Mutschler - 26 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications. With millions of different embedded products, all with different sets of software, it comes down to pr... » read more

‘Good’ Vs. ‘Good Enough’

By Ed Sperling - 22 Jul, 2010 - Comments: 0

By Ed Sperling The decision for when a chip is ready for tapeout is changing—both in time and sometimes in terms of who’s actually making that decision—as the amount of software being developed by hardware companies continues to grow. At the root of this shift are two very different concepts about what constitutes a market-ready product. For SoC engineers, fixing bugs after a chip has... » read more

The Future Of IP

By Ed Sperling - 24 Jun, 2010 - Comments: 0

By Ed Sperling The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP. In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exac... » read more

Synopsys Plus Virage: Combinatorics Or Common Sense?

By Jack Harding - 24 Jun, 2010 - Comments: 0

By Jack Harding It should be no surprise. The industry has been consolidating and expanding and consolidating for nearly 40 years. So when Virage Logic was gobbled up by Synopsys and Denali was ingested by Cadence, it is really a lot more of the same. Or is it? There is a difference. Synopsys has made it crystal clear that its definition of EDA now permanently includes IP. Not that acquirin... » read more

Special Report: Using FPGAs For 3D Stacking

By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

IP Integration Creates Challenges For Power

By Ed Sperling - 13 May, 2010 - Comments: 0

By Ann Steffora Mutschler Managing power when integrating IP is becoming a critical issue at advanced process nodes—and the problem is getting worse. For starters, static power leakage that occurs when the transistors are “off” gets worse at each node. On top of that, multiple states to minimize dynamic power leakage have pushed complexity even further. Throw in third-party IP from m... » read more

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