IP Integration Creates Challenges For Power

Leakage, multiple vendors and multiple power islands combine to make power an even thornier problem at advanced process nodes.


By Ann Steffora Mutschler
Managing power when integrating IP is becoming a critical issue at advanced process nodes—and the problem is getting worse.

For starters, static power leakage that occurs when the transistors are “off” gets worse at each node. On top of that, multiple states to minimize dynamic power leakage have pushed complexity even further. Throw in third-party IP from multiple sources and a couple of different power formats and the problem is magnified yet again.

When integrating IP in advanced technologies, the No. 1 challenge these days is dealing with power, said John Heinlein, vice president of marketing for the physical IP division at ARM. As a result, engineering teams are exposing complexity at the chip design level with things like power gating that they never had to deal with before, which is making overall designs more complicated.

With these design complexities in mind, how do engineers complete their designs? ARM has begun offering foundational EDA support to enable that complexity and supports the Common Power Format supported by Cadence and the Unified Power Format supported by Synopsys and Mentor Graphics. As such, ARM aims to enable engineering teams by offering a “rich and diverse” set of EDA views to customers so they can use the advanced technology they need, Heinlein explained.

Based on experience with power-hungry mobile application processors, Sonics’ Jack Browne, senior VP of sales and marketing, said engineers are struggling to architect systems with multiple voltage and multiple frequency domains, because in order to extend battery life, the subsystems not in use need to be shut off and gated so that even that leakage power goes away. Browne noted that Sonics customers routinely design chips with a dozen power domains and some customers even have designs with 25 to 30 power domains in one chip.

“Being able to manage complexity is important. One of the things that we do in our technology is look at the interconnect as a network that connects to initiators that start to move traffic as well as targets like memory or peripherals that receive out,” Browne said. “Say an initiator starts a burst of some link. You don’t just go in and turn the core off in the middle of a process. You’ve got to wait until the burst finishes or you might break the DRAM subsystem or the flash subsystem because you are not refreshing the right amount of data. And so we’ve got handshakes that say, ‘I’ve started a transfer, I’ve finished a transfer,’ and we let people do full closed loop design around these handshakes.”

Additionally, Frank Ferro, director of business development at Sonics pointed out that within the Sonics tools themselves, the power formats are mostly automated from the standpoint of what the customer is trying to solve. “The interconnect is really the center of the chip where all the cores are connected, so to go in there and design clock domains and power domains with very low idle power, our tools actually take care of that transparently to the user so they don’t have to do a lot of design work there,” he said. This avoids having the engineer manually figure out which clocks should be running and which should be turned off.

While many IP vendors are knee deep in power management techniques such as voltage islands, clock gating, etc., Tensilica looks at things from the SoC level, as its processors are not implemented as application processors, but rather in deeply embedded dataplane-type applications, which are only run at certain times.

“We are normally a power domain unto ourselves so there is a larger SOC integration issue,” said Chris Jones, director of product marketing at Tensilica. “From our perspective, we also do things at the RTL level to minimize the amount of switching logic at any particular time. We employ very fine-grained clock gating, functional clock gating and various low-power modes like shutdown, hibernate, and things like that. What we see that our customers are facing is more of an overall SOC power issue — certainly with leakage in the lower process geometries and we are doing things there to try to completely shut down areas of the processor when they are not in use,” Jones added.

In addition to power, software is a huge challenge in IP integration. Kevin Kitagawa, director of strategic marketing for MIPS Technologies, said that with the integration of richer software environments and open systems (like Google’s Android platform), there are additional issues to address.

“It used to be that, especially on the embedded side, RTOSes or very proprietary operating systems were the way that you went and you shipped a particular system. But now, with much more open systems like Android, there are challenges,” he said. “The rapid movement of open-source, the development of those particular platforms and getting products out the door [is a big challenge] because you can constantly enhance and use the newest versions and that sort of thing, but then you’ll constantly be in a development cycle. So how do you make a decision, put your foot in the ground, lock down on a release, get it working and ship it out the door?”

It often comes down to deciding if it is worth the opportunity cost that you will be losing by waiting for, for example, the next release, he said.