Inside Inspection And Metrology

By Mark LaPedus - 18 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about inspection, metrology and other issues with Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. What follows are excerpts of that conversation. SE: Today, the industry is working on a new range of complex architectures, such as 3D NAND and finFETs. For these technologies, the industry is clearly struggling... » read more

Betting On Wright’s Law

By Imec - 17 Dec, 2015 - Comments: 0

By Paul Heremans Most people know Moore’s Law as "the number of transistors on a chip doubles every two years." That interpretation was the consequence of economic considerations. Moore predicted that "the number of transistors on a chip will rise exponentially if the surface area stays the same, because that way the cost per unit of computing power for integrated transistors will decrease... » read more

Inside The SRC

By Mark LaPedus - 17 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk with Ken Hansen, the new president and chief executive of the Semiconductor Research Corp. (SRC), a U.S.-based technology research consortium. Prior to joining the SRC in May, Hansen was vice president and chief technology officer at Freescale. What follows are excerpts of that conversation. SE: My impression is that the SRC allocates funding for va... » read more

Rethinking Memory

By Ed Sperling - 16 Dec, 2015 - Comments: 3

Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

The Pain Of Change

By Ed Sperling - 24 Nov, 2015 - Comments: 0

If the still evolving shift left has taught the semiconductor industry anything, it's that nothing can be counted on to stay the same for very long. The basic proposition of doing more earlier in the design cycle to speed up time to market—and thereby shifting everything left in the linear flow—means that every silo that has been constructed over the past several decades needs to be rethoug... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 20 Nov, 2015 - Comments: 0

Is Moore’s Law alive or dead? That’s still a topic for debate. In any case, chipmakers continue to move to advanced nodes, but the transitions are taking longer. Even mighty Intel is struggling, based on what the company said about its 14nm finFET process during an investors meeting this week. In fact, Intel continues to struggle with its yields. “14nm yield is maturing; 14nm is still not... » read more

Can Nano-Patterning Save Moore’s Law?

By Mark LaPedus - 19 Nov, 2015 - Comments: 0

For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry. With R&D funding from Intel and others, selective deposition, sometimes called ALD-e... » read more

Why Packaging Matters

By Ed Sperling - 19 Nov, 2015 - Comments: 1

The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

What Comes Next

By Imec - 19 Nov, 2015 - Comments: 0

By Marc Heyns I’m very optimistic about the continuation of Moore’s Law. But in saying that, I’m speaking about Moore’s Law purely as an economic law. I believe we’ll be able to offer increasing amounts of functionality at lower and lower costs. And technological innovations as well as advances in design and application will be crucial in realizing this. But I don’t believe a ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?