3D Integration: Extending Moore’s Law Into The Next Decade

By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

Thinking Digital To Design Analog, And Vice Versa

By Ed Sperling - 27 Mar, 2009 - Comments: 0

By Ed Sperling Until several years ago, analog was a world apart from digital. Analog engineers could comfortably avoid many of the issues of Moore’s Law, viewing it as a costly bad habit with an equally bad outcome. Most analog engineers gloated privately that they could still develop chips at 250nm, or at worst 130nm, while their digital counterparts were struggling to keep up with is... » read more

NoC Your SoCs Off

By Ed Sperling - 19 Feb, 2009 - Comments: 0

By Ed Sperling The network on a chip (NoC) approach is gaining ground as an essential part of a system on a chip (SoC), providing the same kind of time-to-market advantage that well-tested intellectual property blocks provide. This follows almost eight years of hype about NoCs potential with little to show for it. Times have changed and there appear to be two main drivers, one technological a... » read more

The Quest For Faster Data Throughput On A Chip

By Ed Sperling - 19 Feb, 2009 - Comments: 0

By Ed Sperling As with all network topologies, the general rule is the faster the better. Jack Browne, VP of sales and marketing at Sonics, said his customers are asking for higher-speed interconnects. “Right now we’re at 300MHz,” he said. “They want to more than double that in the very near future and eventually get to 1GHz.” Getting to that speed is no simple ... » read more

The Trouble With On-Chip Interfaces

By Ed Sperling - 17 Dec, 2008 - Comments: 0

By Ed Sperling The trouble with standards is that many of them arise out of need rather than through careful planning, and often unilaterally. The typical scenario in chip design is that a company has an issue to solve, so it comes up with a solution. When it gets what it believes is critical mass behind the standard, the company that developed the solution opens it up to the rest of the ind... » read more

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tag: SoC

3D Integration: Extending Moore’s Law Into The Next Decade

Thinking Digital To Design Analog, And Vice Versa

NoC Your SoCs Off

The Quest For Faster Data Throughput On A Chip

The Trouble With On-Chip Interfaces

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