tag: test

From Lab To Fab: Increasing Pressure To Fuse IC Processes
By Gregory Haley - 06 Jun, 2023 - Comments: 0

Test, metrology, and inspection are essential for both the lab and the fab, but fusing them together so that data created in one is easily transferred to the other is a massive challenge. The chip industry has been striving to bridge these separate worlds for years, but the economics, speed, and complexity of change require a new approach. The never-ending push toward smaller, better-defined... » read more

Ramping Up Power Electronics For EVs
By Anne Meixner - 06 Jun, 2023 - Comments: 0

The rapid acceleration of the power devices used in electric vehicles (EVs) is challenging chipmakers to adequately screen the ICs that power these vehicles.[1] While progress toward autonomous driving is grabbing the public’s attention, the electrification of transportation systems is progressing quietly. For the automotive industry, this shift involves a mix of electronic components. Amo... » read more

Power-Supply Card Targets High-Voltage PMIC Test
By Toni Dircherl - 06 Jun, 2023 - Comments: 0

The electronics industry is seeing a move toward higher voltages and currents to deliver sufficient supply and charging power in products ranging from handheld cellphones and tablets to workstations. This trend is evidenced in examples such as the many USB power-delivery (PD) profiles with ratings ranging from 10W (5V at 2A for USB PD 3.0 profile 1) up to 100W (5V at 2A, 12V at 5A, and 20V at 5... » read more

Testing High Power Discrete Devices
By Tom Tran - 06 Jun, 2023 - Comments: 0

Emerging markets are driving the evolution of discrete power devices. Increased power requirements mean more power is being driven through a smaller device, creating challenges in both device design and test. This video series, 3 for 3, provides 3 answers for 3 pressing questions about trends in semiconductor test, and how testing for high power discrete devices is evolving. » read more

From Known Good Die To Known Good System With UCIe IP
By Manuel Mota - 11 May, 2023 - Comments: 0

Multi-die systems are made up of several specialized functional dies (or chiplets) that are assembled in the same package to create the complete system. Multi-die systems have recently emerged as a solution to overcome the slowing down of Moore’s law by providing a path to scaling functionality in the packaged chip in a way that is manufacturable with good yield. Additionally, multi-die sy... » read more

Data Analytics For The Chiplet Era
By Shinji Hioki - 09 May, 2023 - Comments: 0

This article is based on a paper presented at SEMICON Japan 2022. Moore’s Law has provided the semiconductor industry’s marching orders for device advancement over the past five decades. Chipmakers were successful in continually finding ways to shrink the transistor, which enabled fitting more circuits into a smaller space while keeping costs down. Today, however, Moore’s Law is slowin... » read more

The Data Revolution Of Semiconductor Production
By Nitza Basoco - 09 May, 2023 - Comments: 0

During our insightful panel discussion on “The Data Revolution of Semiconductor Production – How Advancements in Technology Unlock New Insights,” we covered several topics including machine learning, edge computing and cloud-based data management. We discussed questions including: Are we creating the right data and doing enough with it? What needs to be done to make data actionable? Ho... » read more

Silicon Lifecycle Management Advances With Unified Analytics
By Guy Cortez - 25 Apr, 2023 - Comments: 0

In a typical day in the life of a product engineer, they have gone through the requisite wafer sort testing in manufacturing with the next step to assemble the resultant good die into their respective packages. While performing a series of parametric tests during final test, yield issues are encountered and the process of finding the source of the issues begins. Luckily, with access to a good d... » read more

Using Machine Learning To Increase Yield And Lower Packaging Costs
By Melvin Lee - 11 Apr, 2023 - Comments: 0

Packaging is becoming more and more challenging and costly. Whether the reason is substrate shortages or the increased complexity of packages themselves, outsourced semiconductor assembly and test (OSAT) houses have to spend more money, more time and more resources on assembly and testing. As such, one of the more important challenges facing OSATs today is managing die that pass testing at the ... » read more

Power-Aware Test: Beyond Low-Power Test
By Rahul Singhal - 11 Apr, 2023 - Comments: 0

By Rahul Singhal and Likith Kumar Manchukonda Power consumption is one of the key considerations when designing today’s semiconductor chips and systems. Over the years, the constant need for higher performance and more functions from the chips has been driving the continuous requirement for higher transistor density. The process node scaling makes this possible by reducing transistor sizes... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy