tag: abstraction levels

The Trouble With Abstractions
By Ann Mutschler - 27 Aug, 2015 - Comments: 0

Ask chip engineers about the value of abstractions and you're likely to get a spectrum of answers. While abstractions help in seeing the big picture on complex designs, the data for performance and power needs to be annotated from detailed information the engineering team may obtain later in the design flow. There is valuable information that can come from using abstractions correctly. And ... » read more

A Different Kind Of Sales Job
By Ed Sperling - 30 Jan, 2014 - Comments: 0

For years EDA companies have been pitching the benefits of ESL tools and high-level modeling, and for just as many years chipmakers have been throwing that idea back at tools vendors saying it’s too expensive to retool. Talks between the two have waffled between polite bickering and contentious negotiations. Chipmakers have approached these “talks” from the stronger bargaining position... » read more

Experts At The Table: The Future Of Verification
By Ed Sperling - 24 Oct, 2013 - Comments: 0

Semiconductor Engineering sat down to discuss the future of verification with Janick Bergeron, Synopsys fellow; Harry Foster, chief verification scientist at Mentor Graphics; Frank Schirrmeister, group director of product marketing for the Cadence System Development Suite; Prakash Narain, president and CEO of Real Intent; and Yunshan Zhu, vice president of new technologies at Atrenta. What foll... » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 28 Jun, 2012 - Comments: 1

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

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