tag: Actel

AMD Wants An FPGA Company, Too
By Ed Sperling - 28 Oct, 2020 - Comments: 0

AMD signed a definitive agreement to acquire Xilinx for $35 billion in stock, setting the stage for a head-to-head battle against Intel in nearly all major markets. But there's more to this acquisition than just keeping up with AMD's arch-competitor. To begin with, the acquisition has a big impact on the programmable logic market. The only pure-play FPGA vendors left are Lattice, Achronix, a... » read more

The Battle To Embed The FPGA
By Brian Bailey - 31 Oct, 2016 - Comments: 1

There have been many attempts to embed an [gettech id="31071" comment="FPGA"] into chips in the past, but the market has failed to materialize—or the solutions have failed to inspire. An early example was [getentity id="22924" comment="Triscend"], founded in 1997 and acquired by [getentity id="22839" e_name="Xilinx"] in 2004. It integrated a CPU—which varied from an [getentity id="22186" co... » read more

Can IP Be Standardized In Low-Power Designs?
By Ed Sperling - 12 Aug, 2010 - Comments: 0

By Ann Steffora Mutschler SoC designers are beginning to embrace low power formats UPF (IEEE P1801) and the Common Power Format (CPF) to express power intent, but are these efforts enough to create standardized IP in low power designs? Mike Brogley, IP and solutions product marketing manager at Actel, believes it is possible. “Yes, IP can be standardized, but the main driver in low-pow... » read more

Special Report: Using FPGAs For 3D Stacking
By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Xilinx is developing a 3D architecture for its FPGAs and Actel has been approached by SoC makers to use its flash-based FPGA as a layer in a 3D IC stack. Both approaches could radically alter the fundamental equation about the tradeoffs between FPGAs and ASICs—particularly the power and performance overhead normally associated with programmable logic. Xilinx declined to com... » read more

Integrated IP Goes Vertical
By Ed Sperling - 25 Mar, 2010 - Comments: 0

By Ed Sperling The consolidation of intellectual property from small developers to large players with integrated IP blocks is accelerating. Large IP companies are now developing integrated suites that are pre-tested for specific vertical markets, and new companies are sprouting up to make it easier to put even broader collections of IP together in meaningful ways. It’s difficult to te... » read more

The Long And Painful Path To Power Optimization
By Ed Sperling - 11 Mar, 2010 - Comments: 0

By Ed Sperling Think about any mobile Internet device today. Batteries typically last all day, applications shut down with ease, and the number of things it can do has reached the point where many people typically carry one device on the road rather than multiple devices they used to lug around several years ago. Perhaps even more astounding is the price drop on these devices. A basic cell ... » read more

New Forces For Consolidation
By Ed Sperling - 05 Mar, 2010 - Comments: 0

For the past five-plus decades, the overriding effect of Moore’s Law was to put more circuits on a single piece of silicon. While that’s still the case, the addition of multiple cores since 90nm also has meant more functions can be added to that chip, which creates a whole new business equation for makers of complex devices like smart phones. Instead of creating individual chips, a single... » read more

The Bright—And Much Larger—Future
By Ed Sperling - 01 Mar, 2010 - Comments: 0

The recent pushes by both Synopsys and Mentor into new markets should say something about the state of EDA. Being able to lay out the wires and subsystems on a chip, not to mention verifying that it all works, will always be vital to getting SoCs to tapeout. But that kind of work will not generate the kind of growth the big EDA companies are looking for—at least not without some major tweaks ... » read more

Experts At The Table: The Reliability Factor
By Ed Sperling - 28 Jan, 2010 - Comments: 0

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation. LPE: Is a more complex supply chain cau... » read more

Experts At The Table: The Reliability Factor
By Ed Sperling - 22 Jan, 2010 - Comments: 0

Low-Power Engineering sat down to discuss reliability with Ken O’Neill, director of high-reliability product marketing at Actel; Brani Buric, executive vice president at Virage Logic; Bob Smith, vice president of marketing at Magma, and John Sanguinetti, chief technology officer at Forte Design Systems. What follows are excerpts of that conversation. LPE: As we push to the next process nod... » read more

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