Simulation Closes Gap Between Chip Design Optimization And Manufacturability


Simulation is playing an increasingly critical and central role throughout the design-through-manufacturing flow, fusing together everything from design to manufacturing and test in order to reduce the number and cost of silicon respins. The sheer density of modern chips, combined with advanced packaging techniques like 3D stacking and heterogeneous integration, has made iterative physical p... » read more

Early Detection Of C-RES Degradation On High-Current Power Planes


Probe-card or device contactor damage can be dramatic and catastrophic, with yield dropping drastically very quickly. What is not dramatic is the hypothesized slow probe needle or contactor degradation process that might precede catastrophic failure. Such degradation is difficult to detect in the early stages, when probe cards, die, and packages continue to yield normally. A key goal is to dete... » read more

Chip Industry Week In Review


The chip industry is well on its way to hit $1 trillion in revenue by the end of its decade. Several analyst firms released 2024 annual results and 2025 predictions: Worldwide semiconductor revenue reached $626 billion in 2024, an 18% increase versus 2023, according to preliminary Gartner report. Memory revenue grew about 70%  2024 versus 2023. The firm forecasts that HBM will make up 19%... » read more

Using Test And Metrology Data For Dynamic Process Control


Advanced packaging is transforming semiconductor manufacturing into a multi-dimensional challenge, blending 2D front-end wafer fabrication with 2.5D/3D assemblies, high-frequency device characterization, and complex yield optimization strategies. These combinations are essential to improving performance and functionality, but they create some thorny issues for which there are no easy fixes. ... » read more

Screening For Known Good Interposers


Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package. Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus... » read more

Experiences Estimating Test Quality And Test Escape Rates


When discussing product quality in integrated circuits (ICs), two key aspects are essential: time zero defects and reliability. These concepts help distinguish between issues that appear immediately after manufacturing and those that occur over time. Understanding these distinctions is critical for ensuring that products meet the quality demands of their respective markets, particularly in h... » read more

DFT At The Leading Edge


Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed interfaces, and lifecycle data analytics, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; D... » read more

Chip Industry Week In Review


Global semiconductor sales hit $57.8 billion in November 2024, an increase of 20.7% compared to the same month last year, according to the Semiconductor Industry Association. In U.S. government news: The U.S. Department of Commerce finalized up to $325 million in CHIPS Act funding for Hemlock Semiconductor, which will support construction of a new semiconductor-grade polysilicon manufac... » read more

Shortcutting Graduates’ Path To Productivity In Manufacturing And Test


Manufacturing, test, assembly, and analytics companies are finding unique ways to engage with universities in an effort to shore up the talent pipeline. The industry is recruiting graduates from universities across the U.S. while partnering with local institutes to serve specific needs. Industry/university co-operation includes: Mapping job descriptions Providing curricula frameworks... » read more

Chip Industry Week In Review


The 2024 IEEE International Electron Devices Meeting (IEDM) was held this week, prompting a number of announcements from: imec: Proposed a new CFET-based standard cell architecture for the A7 node containing two rows of CFETs with a shared signal routing wall in between, allowing standard cell heights to be reduced from 4 to 3.5T, compared to single-row CFETs. Integrated indium pho... » read more

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