Chip Industry Week In Review


By Jesse Allen, Susan Rambo, and Liz Allan The U.S. government will invest about $3 billion for the National Advanced Packaging Manufacturing Program (NAPMP), including an advanced packaging piloting facility to help U.S. manufacturers adopt new technology and workforce training programs. It also will provide funding for projects concentrating on materials and substrates; equipment, tools, ... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Blog Review: November 15


Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

DRAM Test And Inspection Just Gets Tougher


DRAM manufacturers continue to demand cost-effective solutions for screening and process improvement amid growing concerns over defects and process variability, but meeting that demand is becoming much more difficult with the rollout of faster interfaces and multi-chip packages. DRAM plays a key role in a wide variety of electronic devices, from phones and PCs to ECUs in cars and servers ins... » read more

Rebalancing Test And Yield In IC Manufacturing


Balancing yield and test is essential to semiconductor manufacturing, but it's becoming harder to determine how much weight to give one versus the other as chips become more specialized for different applications. Yield focuses on maximizing the number of functional chips from a production batch, while test aims to ensure that each chip meets rigorous quality and performance standards. And w... » read more

Chip Industry Week In Review


By Susan Rambo, Karen Heyman, and Liz Allan The Biden-Harris administration designated 31 Tech Hubs across the U.S. this week, focused on industries including autonomous systems, quantum computing, biotechnology, precision medicine, clean energy advancement, and semiconductor manufacturing. The Department of Commerce (DOC) also launched its second Tech Hubs Notice of Funding Opportunity. ... » read more

Chip Industry Talent Shortage Drives Academic Partnerships


Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Using Smart Data To Boost Semiconductor Reliability


The chip industry is looking to AI and data analytics to improve yield, operational efficiency, and reduce the overall cost of designing and manufacturing complex devices. In fact, SEMI estimates its members could capture more than $60B in revenues associated through smart data use and AI. Getting there, however, requires overcoming a number of persistent obstacles. Smart data utilization is... » read more

Integration Challenges For ATE Data


Tighter integration of automatic test equipment (ATE) into semiconductor manufacturing, so that data from one process can be seamlessly leveraged by another, holds significant promise to boost manufacturing efficiency and yield. The challenge is selling this concept to fabs, packaging houses, and their customers. Data involving yield parameters, process variations, and intricate details abou... » read more

Comparison Of State-Of-The-Art Models For Socket Pin Defect Detection


This article is adapted from a presentation at TestConX, March 5-8, 2023, Mesa, AZ, by Vijayakumar Thangamariappan, Nidhi Agrawal, Jason Kim, Constantinos Xanthopoulos, Ira Leventhal, and Ken Butler, Advantest America Inc., and Joe Xiao, Essai, Advantest Group. Test sockets have a key role to play in the semiconductor test industry. A socket serves as the critical interface between a teste... » read more

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