DTCO/STCO Create Path For Faster Yield Ramps


Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

AI/ML Challenges In Test and Metrology


The integration of artificial intelligence and machine learning (AI/ML) into semiconductor test and metrology is redefining the landscape for chip fabrication, which will be essential at advanced nodes and in increasingly dense advanced packages. Fabs today are inundated by vast amounts of data collected across multiple manufacturing processes, and AI/ML solutions are viewed as essential for... » read more

Strategies For Detecting Sources Of Silent Data Corruption


Engineering teams are wrestling with how to identify the root causes of silent data corruption (SDC) in a timely and cost-effective way, but the solutions are turning out to be broader and more complex than simply fixing a single defect. This is particularly vexing for data center reliability, accessibility and serviceability (RAS) engineering teams, because even the best tools and methodolo... » read more

Blog Review: Feb. 14


Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Adaptive Test Ramps For Data Intelligence Era


Widely available and nearly unlimited compute resources, coupled with the availability of sophisticated algorithms, are opening the door to adaptive testing. But the speed at which this testing approach is adopted will continue to vary due to persistent concerns about data sharing and the potential for IP theft and data leakage. Adaptive testing is all about making timely changes to a test p... » read more

Hidden Costs And Tradeoffs In IC Quality


Balancing reliability against cost is becoming more difficult for semiconductor test, as chip complexity increases and devices become more domain-specific. Tests need to be efficient and effective without breaking the bank, while also ensuring chips are of sufficient quality for their specific application. The problem is that every new IC device adds its own set of challenges, from smaller f... » read more

True Zero Trust Combats IC Manufacturing Security Challenges


The semiconductor manufacturing industry is facing a host of unprecedented technology and security challenges. A common catchphrase these days is that “data is the new oil.” Data is everywhere, in everything we do, and there is both good and bad associated with this trend. Data everywhere creates new security issues that need to be addressed to protect the integrity of your information and ... » read more

Blog Review: Jan. 10


Keysight’s Jenn Mullen explains how ChatGPT’s tools can help quality assurance (QA) engineers and software testers overcome test automation debt, and become more productive and able to deliver consistently high-quality products to market faster. Siemens’ Keith Felton discusses how the paradigm of “shift-left” power delivery analysis has emerged as a critical methodology in addressi... » read more

Glass Substrates Gain Foothold In Advanced Packages


Glass substrates are starting to gain traction in advanced packages, fueled by the potential for denser routing and higher signal performance than the organic substrates used today. There are still plenty of problems to solve before this approach becomes mainstream. While glass itself is cheap and shares some important physical similarities to silicon, there are challenges with buildup, stre... » read more

Plugging Gaps In The IC Supply Chain


Multiple touch points in manufacturing and packaging are exposing gaps in the data used to track different components, making it difficult to identify the source of issues that can affect yield and reliability, and opening the door to counterfeit or sub-standard parts. This involves more than just assigning a simple identifying code to a chip. At different points in a device's lifecycle, new... » read more

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