Using Machine Learning In EDA

By Ann Mutschler - 02 Aug, 2017 - Comments: 0

Machine learning is beginning to have an impact on the EDA tools business, cutting the cost of designs by allowing tools to suggest solutions to common problems that would take design teams weeks or even months to work through. This reduces the cost of designs. It also potentially expands the market for EDA tools, opening the door to even new design starts and more chips from more compan... » read more

The Efficiency Problem

By Samer Hijazi - 11 May, 2017 - Comments: 0

Part one of this report addressed the efficiency problem in neural networks. This segment addresses efficiencies in training, quantization, and optimizing the network and the hardware. Minimize the Bits (CNN Advanced Quantization) Training a CNN involves assigning weight vectors to certain results, and applying adaptive filters to those results to determine the positives, false positives, a... » read more

Speeding Up Neural Networks

By Ed Sperling - 27 Apr, 2017 - Comments: 2

Neural networking is gaining traction as the best way of collecting and moving critical data from the physical world and processing it in the digital world. Now the question is how to speed up this whole process. But it isn't a straightforward engineering challenge. Neural networking itself is in a state of almost constant flux and development, which makes it something of a moving target. Th... » read more

Teaching Computers To See

By Ann Mutschler - 16 Nov, 2016 - Comments: 0

Vision processing is emerging as a foundation technology for a number of high-growth applications, spurring a wave of intensive research to reduce power, improve performance, and push embedded vision into the mainstream to leverage economies of scale. What began as a relatively modest development effort has turned into an all-out race for a piece of this market, and for good reason. Mark... » read more

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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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Using Machine Learning In EDA

The Efficiency Problem

Speeding Up Neural Networks

Teaching Computers To See

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