Chip Industry Week In Review

By The SE Staff - 22 Sep, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan The U.S. Department of Defense (DOD) announced $238 million in awards toward establishing eight regional innovation hubs under the CHIPS and Science Act. The hubs aim to accelerate hardware prototyping and "lab-to-fab" transition of semiconductor technologies for secure edge/IoT, 5G/6G, AI hardware, quantum technology, electromagnetic warfare, and ... » read more

Building Better Bridges In Advanced Packaging

By Laura Peters - 21 Sep, 2023 - Comments: 1

The increasing challenges and rising cost of logic scaling, along with demands for an increasing number of features, are pushing more companies into advanced packaging. And while that opens up a slew of new options, it also is causing widespread confusion over what works best for different processes and technologies. At its core, advanced packaging depends on reliable interconnects, well-def... » read more

Reverse Laser Assisted Bonding (R-LAB) Technology For Chiplet Module Bonding On Substrate

By SeokHo Na - 21 Sep, 2023 - Comments: 0

By SeokHo Na, MinHo Gim, GaHyeon Kim, DongSu Ryu, DongJoo Park, and JinYoung Kim In the recent semiconductor market, there are many applications including smartphone, tablets, central processing units (CPUs), artificial intelligence (AI), data cloud and more that are expecting and experiencing rapid growth. As most of these applications require high performance, single-die Flip Chip packages... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging

By Amkor - 21 Sep, 2023 - Comments: 0

Bridge technology is a promising heterogeneous integration (HI) solution for application-specific integrated circuits (ASICs) and high bandwidth memory (HBM). The bridge dies provide localized communications among the multiple system on chips (SoCs) in a single package. In Amkor's bridge technology, S-Connect provides die-to-die connections with fine pitch [1]. Prototype S-Connect technology wa... » read more

Challenges Of Testing Advanced Packages

By Ed Sperling - 19 Sep, 2023 - Comments: 0

The number of things that can wrong in assembly and test increases as more chips are added into a package. Testing is the usual guarantor of a reliable device, but in an advanced package there are all sorts of new issues — more contacts, different handling requirements, the necessary thermal conditions for test, and variation within the package. George Harris, vice president of global test se... » read more

Securing Chip Manufacturing Against Growing Cyber Threats

By Anne Meixner - 17 Aug, 2023 - Comments: 0

Semiconductor manufacturers are wrestling with how to secure a highly specialized and diverse global supply chain, particularly as the value of their IP and their dependence upon software increases — along with the sophistication and resources of the attackers. Where methodologies and standards do exist for security, they often are confusing, cumbersome, and incomplete. There are plenty of... » read more

Enabling A Chiplet Supply Chain

By Vik Chaudhry - 17 Aug, 2023 - Comments: 0

Chiplets have been in the news quite a bit lately. A chiplet-based architecture offers several advantages that chip designers can benefit from as they bring out new products to the market. Over the years, system designers have integrated more and more functions into a system on chip (SoC). As a result, the size of SoCs keeps increasing. Even though SoCs provide several advantages in performance... » read more

SiC Growth For EVs Is Stressing Manufacturing

By Anne Meixner - 08 Aug, 2023 - Comments: 0

The electrification of vehicles is fueling demand for silicon carbide power ICs, but it also is creating challenges in finding and identifying defects in those chips. Coinciding with this is a growing awareness about just how immature SiC technology is and how much work still needs to be done — and how quickly that has to happen. Automakers are pushing heavily into electric vehicles, and t... » read more

Chiplets: Deep Dive Into Designing, Manufacturing, And Testing

By The SE Staff - 07 Aug, 2023 - Comments: 0

Chiplets are a disruptive technology. They change the way chips are designed, manufactured, tested, packaged, as well as the underlying business relationships and fundamentals. But they also open the door to vast new opportunities for existing chipmakers and startups to create highly customized components and systems for specific use cases and market segments. This LEGO-like approach sounds ... » read more

A Hybrid PLP Technology Based On A 650mm x 650mm Platform

By Eoin O'Toole - 25 Jul, 2023 - Comments: 0

A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package di... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.