tag: AMS

Analog IP Migration Using Design Knowledge Extraction
By Various Writers - 07 Nov, 2013 - Comments: 0

Demonstrated in this paper is a technique for automatic circuit resizing between different technologies. It relies on design knowledge extraction, which renders it very fast compared to full optimization approaches and allows handling of much larger circuits. This technique studies the original design and extracts its major features (basic devices & blocks features, device matching, parasitics,... » read more

Blog Review: Oct. 23
By Ed Sperling - 23 Oct, 2013 - Comments: 0

It was a good week for good questions. Cadence’s Brian Fuller asks what applications dream about—or rather what’s their potential. In the context of technology development, that’s worth pondering. Mentor’s Mike Jensen asks what will you be remembered for. There are a couple other important addendums to that, such as how long you will be remembered. And perhaps even more important, ... » read more

IP-XACT Becoming More Useful
By Ed Sperling - 01 Oct, 2013 - Comments: 0

Accellera created analog/mixed signal extensions to the IEEE IP-XACT standard, and the standards group will recommend an update to the overall standard later this year to make it more useful for IP integration. IP-XACT has been considered a great idea since its introduction in 2009 because it allows IP makers to add metadata to their IP—information needed to integrate it into complex desig... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

Solutions For Mixed-Signal IP, IC, And SoC Implementation
By Various Writers - 28 Mar, 2013 - Comments: 0

Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Realizing modern mixed-signal designs requires new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implem... » read more

Smarter Things
By Ed Sperling - 28 Feb, 2013 - Comments: 0

By Ed Sperling SoC design has largely been a race to the next process node in accordance with Moore’s Law, but it’s about to take a sharp turn away from that as the Internet of Things becomes more ubiquitous. There has been much made about the Internet of Things over the past couple of years—home networks that involve smart refrigerators sending reminders to consumers that the milk is... » read more

Experts At The Table: Obstacles In Low-Power Design
By Ed Sperling - 16 Nov, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss low-power design with with Leah Clark, associate technical director at Broadcom; Richard Trihy, director of design enablement at GlobalFoundries; Venki Venkatesh, engineering director at Atrenta; and Qi Wang, technical marketing group director at Cadence. What follows are excerpts of that conversation. LPHP: What effe... » read more

FPGA Design And Verification in Mechatronic Applications
By Various Writers - 23 Aug, 2012 - Comments: 0

The biggest challenge in using FPGA devices may be one of methodology. FPGA designers are familiar with HDL-based requirements-driven design methodologies for digital electronics. But how can requirements be expressed for a system that, while it contains digital elements, is fundamentally non-digital? Fortunately an executable HDL exists that extends the capabilities of the digital VHDL languag... » read more

Analog Hits The Power Wall
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Analog design teams are starting to encounter the same physical issues that digital design engineers began wrestling with several nodes ago—only the problems are more complicated and even more difficult to solve. At advanced nodes digital circuitry is susceptible to an array of physical effects ranging from heat, electromigration, electromagnetic interference and electrosta... » read more

The Challenges Of 28nm HKMG
By Various Writers - 26 Jun, 2012 - Comments: 0

28nm Super Low Power (28nm-SLP) is the low power CMOS offering delivered on a bulk silicon substrate for mobile consumer and digital consumer applications. This technology has four Vt's (high, regular, low and super low) for design flexibility with multi-channel length capability and offers the ultimate in small die size and low cost. Multiple SRAM bit cells for high density and high-performanc... » read more

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