The Four Pillars Of Hyperscale Computing

By Frank Schirrmeister - 27 Aug, 2020 - Comments: 0

In his keynote at CadenceLIVE Americas 2020, Facebook’s Vijay Rao, director, Technology and Strategy, described the four core elements the team considers when designing their data centers—compute, storage, memory, and networking. Wait a minute. Facebook? How did we get here? Wasn’t EDA supposed to be focused on chip design? As indicated in a previous blog, electronic value chains are defi... » read more

System Bits: July 3

By Ann Mutschler - 03 Jul, 2017 - Comments: 0

VW emissions tests cheat code found A team of researchers from UC San Diego, Ruhr University along with an independent researcher has uncovered the mechanism that Volkswagen used to circumvent U.S. and European emission tests over a period of at least six years before the EPA put the company on notice in 2015 for violating the Clean Air Act. The researchers found the code that allowed onboa... » read more

New Twist On Scalable Electronics?

By Brian Fuller - 14 Mar, 2016 - Comments: 0

Snug in their tents at Everest base camp a few years ago, Matt Du Puy and his colleagues marveled at the howling snowstorm outside, until they peeked out and saw snow drifts piling up quickly. They made a quick decision to tug on their boots and seek safer ground. As they did, clutches of other campers emerged and fell in line, bleary-eyed refugees trudging through the darkness. “We got of... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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The Four Pillars Of Hyperscale Computing

System Bits: July 3

New Twist On Scalable Electronics?