Can You Build A Known-Good Multi-Die System?


Semiconductor Engineering sat down to discuss the challenges of designing and testing multi-die systems, including how to ensure they will work as expected, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Zeng, senior engineering group director at Cadenc... » read more

Blog Review: June 18


Synopsys’ John Koeter and other industry experts discuss whether high-bandwidth memory should follow established standards for broad compatibility and scalability or be customized to address specific use case requirements and time-to-market targets. In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about how progress in 3D-IC development, thermal management, and the indu... » read more

Chip Industry Week in Review


The Chinese Academy of Sciences unveiled a fully automated processor chip design system, claiming the potential to accelerate semiconductor development and replace human programmers. Micron Technology plans to expand its U.S. investments to approximately $150 billion in domestic memory manufacturing and $50 billion in R&D, which is $30 billion higher than previously reported. AMD laun... » read more

Simplify Simulation With Reduced-Order Modeling


One of the biggest challenges in engineering and design is striking a balance between accuracy and speed. Development teams strive for precision but must often accelerate their simulation and computational workflows to meet production demands. Although physics-based, high-fidelity simulations are highly accurate, they are computationally expensive in terms of time and resources due to their com... » read more

Multi-Die Assemblies Complicate Parasitic Extraction


The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

Introducing a Digital Engineering Methodology To Aid All Engineers


A systems engineer developing a novel system-on-a-chip (SoC) design. A CFD engineer studying the airflow over the wing of a new electric airplane design. A safety engineer reviewing the design of a new pacemaker to confirm that it is compliant with existing regulations and requirements. What do all these people have in common? One connecting thread is the ever-present need to efficiently col... » read more

Mobile Chip Challenges In The AI Era


Leading smart phone vendors are struggling to keep pace with the rising compute and power demands of localized generative AI, standard phone functions, and the need to move more data back and forth between handsets and the cloud. In addition to edge functions, such as facial recognition and other on-device apps, phones must accommodate a continuous stream of new communications protocols, and... » read more

AR/VR Glasses Taking Shape With New Chips


More augmented reality (AR), virtual reality (VR), and mixed reality (MR) wearables are coming, but how they are connected, and where image and other data is processed, are still in flux. Ray-Ban Meta AI glasses, for example, look like classic eyeglasses, but they rely on a tethered smart phone for such functions as taking pictures, AI voice assistance, and object identification. In contrast... » read more

Blog Review: June 4


In a podcast, Siemens’ Conor Peick, Dale Tutt, and Mike Ellow chat about the implications of the software-defined transition, how it affects semiconductor development, and why it seems to be leading more companies towards developing their own silicon. Cadence’s Vinod Khera shows off a Linux-based audio development platform for prototyping AI audio applications with support for real-time ... » read more

Chip Industry Week in Review


The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

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