tag: Apache Design Solutions

Power Delivery Network Verification Coverage
By Ansys - 03 Dec, 2014 - Comments: 0

Power grid verification is a challenge, and there are no industry standards for design teams to follow that will verify the power grid for power and signal integrity issues. In other areas there is typically a verification plan with checks to perform, and when successfully completed, the design is then considered verified to proceed to tape-out. Having high coverage in the power grid’s power... » read more

Power And Noise Integrity For Analog / Mixed-Signal Designs
By Ansys - 05 Nov, 2014 - Comments: 0

The convergence of advance process technology, increasing levels of integration, and higher operating frequencies pose considerable challenge to IP designers whose circuits are required to function in variety of conditions. Full-custom and mixed signal circuit designers ensure that their circuits will function by simulating for various operating conditions (PVT, input stimuli, etc). One key asp... » read more

Making Chips Run Faster
By Ed Sperling - 11 Sep, 2014 - Comments: 3

For all the talk about low power, the real focus of most chipmakers is still performance. The reality is that OEMs might be willing to sacrifice increasing performance for longer battery life, but they will rarely lower performance to reach that goal. This is more obvious for some applications than others. A machine monitor probably isn’t the place where performance will make much of a dif... » read more

Limiters To The Internet Of Things
By Brian Bailey - 11 Sep, 2014 - Comments: 0

“Specialization is for insects.” Robert A. Heinlein, Time Enough for Love In many respects, the [getkc id="76" kc_name="Internet of Things"] (IoT) is already here. But because most of it is not directed at the consumer space, it seamlessly blends into the environment, unnoticed by everyone except for those who are reaping the benefits of it. When we talk about the IoT, most people concentr... » read more

IoT Brings Low Power To Forefront
By Brian Bailey - 11 Sep, 2014 - Comments: 0

Low power has become a primary design consideration over the past decade, driven by consumer portable devices packing in greater amounts of processing power and sophisticated communications, while at the same time providing extended battery life even though developments in battery technology have advanced little in the same timeframe. But the [getkc id="76" comment="Internet of Things"] (IoT) w... » read more

A Tale Of Two Standards
By Ed Sperling - 18 Jul, 2013 - Comments: 0

By Ed Sperling It could well be one of the strangest developments in standards history. Two competing standards for power formats were rolled out in the middle of the last decade and aside from a few cries of foul they fell below the radar screen of most chip designers and architects for a half-dozen years. Fast forward to the present and the Common Power Format (CPF) and Unified Power Form... » read more

Experts At The Table: Power Budgeting
By Ed Sperling - 03 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Cary Chin, director of technical marketing for low-power solutions at Synopsys; Vic Kulkarni, general manager of the RTL business unit at Apache Design Solutions; Matt Klein, principal engineer for power and broadcast applications at Xilinx; and Paul ... » read more

Power Budgets: Where Is The Low-Hanging Fruit?
By Ed Sperling - 15 Sep, 2012 - Comments: 0

Low-Power Engineering looks for the best ways to cut power for a reasonable cost with Mentor Graphics, Synopsys, Apache Design Solutions, Oasys Design Systems and Xilinx. [youtube vid=Gqoenm00Mso] » read more

Noise Coupling Analysis
By Arvind Vel - 06 Oct, 2011 - Comments: 0

By Arvind Shanmugaval Integrating digital and mixed-signal IP blocks in SoCs poses a considerable challenge to verification of power/ground and substrate noise. Traditional methods of power supply noise analysis are unable to meet the demands of today’s highly integrated designs with multiple low- power design techniques. Existing methods also do not provide sufficient capacity or the capabi... » read more

Limits For TSVs In 3D Stacks?
By Ed Sperling - 06 Oct, 2011 - Comments: 0

By Ed Sperling Semiconductor design always has been about solving technology issues one node at a time, often in the face of a perpetual barrage of looming problems. In fact, if there is any change at all, it’s in the number of threats that have to be solved now at each node, most of them driven by ever-increasing density and the laws of physics. Stacking die holds the promise of becoming... » read more

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