Automotive Power Concerns

By Ann Steffora Mutschler With advanced semiconductor technologies infiltrating the automotive market in ever new and exciting ways, there are also challenges to implementation involving power. In fact, power has become a concern in many areas of automotive design. Consider the Tesla, for example. The dashboard features a 17” touchscreen with the entire vehicle controls. This system i... » read more

Watching And Waiting For DFP

By Ann Steffora Mutschler Although the semiconductor industry has been talking about the need to optimize SoC designs for power for many years, it is safe to say it’s still in the very early stages of the 'Design for Power' approach. That’s not to say that methodologies and tools are not in place. There are actually a number of options available, depending on the level of abstractio... » read more

The Double Whammy

By Ann Steffora Mutschler Given that at 40nm and below every [getkc id="81" kc_name="SoC"] has some mixed-signal content, combined with the fact that power awareness is top priority no matter what the target application is, design teams and verification engineers are grappling with tremendous challenges just to get a chip to yield. “For verification engineers and for designers, this is a ... » read more

Mining For Data

By Ann Steffora Mutschler Power analysis accuracy at the RTL design abstraction is a challenging problem. Smaller geometries just make the challenge of predicting accurate RTL power consumption even more difficult, which in turn impacts other design decisions such as power-grid planning and package selection. “It’s one of these things where the earlier you are in the design, even befo... » read more

28, 20nm Nodes Demand Advanced Power Management

By Ann Steffora Mutschler With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible. Sub-Clock Power Gating Far from a new techniqu... » read more

Power Modeling: Use Cases Need to be Clearly Defined

By Ann Steffora Mutschler Low-Power/High-Performance Engineering sat down to discuss power modeling during the Design Automation Conference with Vic Kulkarni, senior vice president and general manager at Apache Design; Paul Martin, design enablement and alliances manager at ARM; Sylvan Kaiser, CTO at Docea Power; and Frank Schirrmeister, group director, product marketing for system deve... » read more

The Problem With Proximity

By Ed Sperling At 90nm companies had to begin thinking seriously about how the signals inside a chip would begin interfering with each other. At 40nm and beyond, they have to consider how signals are interfering with each other across an entire device that may include multiple SoCs. This marks an interesting shift in what companies have been calling holistic design for the better part of a ... » read more

Killer Bugs

By Ed Sperling Hardware and software bugs are all around us. When an application suddenly dies or a smart phone freezes because of the unanticipated interaction between hardware and software blocks in a system on chip, most users aren’t even the least bit fazed. They usually just re-boot and forget about it. Bugs caused by power are an entirely different matter, however. For one thing, ... » read more

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