The End Of Silicon?


As transistors shrink, not all device parameters scale at the same rate—and therein lies a potentially huge problem. In recent years, manufacturers have been able to reduce equivalent oxide thickness (EOT) more quickly than operating voltage. As a result, the electric field present in the channel and gate dielectric has been increasing. Moreover, EOT reduction is achieved in part by reduci... » read more

The Week In Review: Manufacturing


After several delays due to a myriad of complex regulatory issues, Applied Materials’ proposed deal to buy Tokyo Electron Ltd. (TEL) has been scrapped. Now, Applied Materials and TEL are separately re-grouping, and are back to where they originally started as competitors in the fab tool market. Applied Materials held a conference call to explain the situation with TEL. Applied Materials... » read more

Analysis: Applied-TEL Scrap Merger


After several delays due to a myriad of complex regulatory issues, Applied Materials’ proposed deal to buy Tokyo Electron Ltd. (TEL) has been scrapped. It appears that the U.S. Department of Justice (DoJ) stepped in and blocked the deal. Now that the deal has been terminated, Applied Materials and TEL are separately re-grouping, and are back to where they originally started as fierce compe... » read more

The Week In Review: Manufacturing


For years, Altera’s sole foundry was TSMC. Then, not long ago, Altera selected Intel as its foundry partner for 14nm. TSMC still handles 20nm and above work for Altera. This quarter, Altera was supposed to select a foundry partner for 10nm. This week, Altera posted lackluster results in the quarter. Altera did not elaborate on its 10nm plans, nor did it discuss the Intel rumors. "Altera did n... » read more

Blog Review: April 22


DARPA thinks machine-brain interfaces are poised to become an industry-changing technology. Rambus' David G. Stork brings us emerging developments in the field from the Neural Engineering Boot Camp. If you live in an area that doesn't get quite enough sun for solar panels, how about a smart window that harvests energy from wind and rain? In this week's top five picks, Ansys' Justin Nescott a... » read more

Manufacturing Bits: April 21


Fan-out packaging consortium A*STAR’s Institute of Microelectronics (IME) and others have formed a high-density fan-out wafer level packaging (FOWLP) consortium in Singapore. Others in the group include Amkor, Nanium, STATS ChipPAC, NXP, GlobalFoundries, Kulicke & Soffa, Applied Materials, Dipsol Chemicals, JSR, KLA-Tencor, Kingyoup Optronics, Orbotech and Tokyo Ohka Kogyo (TOK). T... » read more

The Week In Review: Manufacturing


It could be a long year for the equipment industry. First, Intel reduced its 2015 capital expenditure budget to $8.7 billion, plus or minus $500 million. This is down from the previous mid-point guidance of $10.1 billion. As a result of Intel’s announcement, Pacific Crest Securities cut its worldwide 2015 semiconductor CapEx forecast. The new CapEx forecast is now $62.5 billion in 2015. Th... » read more

New Patterning Paradigm?


Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or br... » read more

Next EUV Challenge: Mask Inspection


Extreme ultraviolet ([gettech id="31045" comment="EUV"]) lithography is still not ready for prime time, but the technology finally is moving in the right direction. The EUV light source, for example, is making progress after years of delays and setbacks. Now, amid a possible breakthrough in EUV, the industry is revisiting a nagging issue and asking a simple question: How do you inspect EUV p... » read more

Flash Dance For Inspection And Metrology


Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

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