RISC-V Pros And Cons

Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation. It has been known for some time that with [getkc id="74" comment="Moore's Law"] not offering the same... » read more

Supporting CPUs Plus FPGAs (Part 3)

While it has been possible to pair a CPU and FPGA for quite some time, two things have changed recently. First, the industry has reduced the latency of the connection between them and second, we now appear to have the killer app for this combination. Semiconductor Engineering sat down to discuss these changes and the state of the tool chain to support this combination, with Kent Orthner, system... » read more

How Cache Coherency Impacts Power, Performance

As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

Will Open-Source Work For Chips?

Open source is getting a second look by the semiconductor industry, driven by the high cost of design at complex nodes along with fragmentation in end markets, which increasingly means that one size or approach no longer fits all. The open source movement, as we know it today, started in the 1980s with the launch of the GNU project, which was about the time the electronic design automation (... » read more

Will The Chip Work?

As the number of possible issues mount for integrating IP into complex chips, so does the focus on solving these issues. What becomes quickly apparent to anyone integrating multiple IP blocks is that one size doesn't fit all, either from an IP or a tools standpoint. There is no single solution because there is no single way of putting IP together. Each architecture is unique, and each brings... » read more

The Week In Review: Design/IoT

Tools Mentor Graphics rolled out a new version of its tool for transferring PCB designs into data for fabrication, assembly and test. The company also announced that its debug environment will support the UPF Low Power Successive Refinement Methodology. Deals Ansys and Cray are claiming the world's record for simulation by scaling 129,000 cores. That's about 4X the previous record.  Ansys... » read more

Leveraging Processor Extensibility To Build An Ultra Low-Power Embedded Subsystem

There is increasing demand for electronic devices to execute more functions while consuming less power and silicon area. To achieve this, systems instantiating multiple, heterogeneous processor cores optimized for low power and high performance are gaining popularity among design teams. In these systems, one or more deeply embedded processors execute a limited set of dedicated applications. The... » read more

The Power-Performance Paradox

The Changing World Technology is shaping and altering the world around us. Reality is being augmented and “virtual reality” is becoming the norm. Video is becoming more immersive, offering 3D effects and 4K resolution, with 8K on the horizon. Cars are a technology showcase that in a few years conceivably will take over the driving for us. Our ability to interact with technology through tou... » read more

Are Processors Running Out Of Steam?

In 2004, Intel introduced a new line of Pentium chips that ran at 3.6GHz. Fast forward to today, and the company’s i7 processors run at 3.5GHz with a Turbo Boost to 3.9GHz. There have been many improvements in the meantime. There is more cache and dramatically faster access to data stored in that cache. And there are more cores with improved coherency between them. But the big problem is p... » read more

The Week In Review: System-Level Design

Cadence bought TranSwitch’s high-speed interface IP assets. TranSwitch, which made chips for communications equipment, filed for bankruptcy in November. (The company’s Web site is no longer active.) Cadence also won a deal with Microsoft, which will use Tensilica processors in the new Xbox One audio subsystem. And Cadence rolled out HiFi Audio Tunneling for Android, which takes advantage of... » read more

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