Sidestepping Lithography In Chip Manufacturing

By Katherine Derbyshire - 23 May, 2024 - Comments: 0

Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Extending Copper Interconnects To 2nm

By Laura Peters - 17 Mar, 2022 - Comments: 0

Transistor scaling is reaching a tipping point at 3nm, where nanosheet FETs will likely replace finFETs to meet performance, power, area, and cost (PPAC) goals. A significant architectural change is similarly being evaluated for copper interconnects at 2nm, a move that would reconfigure the way power is delivered to transistors. This approach relies on so-called buried power rails (BPRs) and... » read more

Where Is Selective Deposition?

By Mark LaPedus - 25 Jun, 2018 - Comments: 4

For years, the industry has been working on an advanced technology called area-selective deposition for chip production at 5nm and beyond. Area-selective deposition, an advanced self-aligned patterning technique, is still in R&D amid a slew of challenges with the technology. But the more advanced forms of technology are beginning to make some progress, possibly inching closer from the la... » read more

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tag: area-selective ALD

Sidestepping Lithography In Chip Manufacturing

Extending Copper Interconnects To 2nm

Where Is Selective Deposition?

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