tag: AT&S

Chip Industry Week In Review
By The SE Staff - 26 Jan, 2024 - Comments: 0

By Jesse Allen, Karen Heyman, and Susan Rambo UMC and Intel will collaborate on the development of a 12nm semiconductor process platform to address high-growth markets, such as mobile, communications infrastructure, and networking. Apple reportedly pushed back the launch date of its long-awaited electric vehicle and scaled back the self-driving features to L2 driver assistance, according ... » read more

Next Steps For Panel-Level Packaging
By Mark LaPedus - 20 Dec, 2021 - Comments: 1

Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Manufacturing Bits: Aug. 24
By Mark LaPedus - 24 Aug, 2021 - Comments: 0

Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

Geopolitical And Economic Outlook For Chips And Equipment
By Ed Sperling - 17 Jun, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss geopolitical and economic changes and how they affect the chip industry with Jean-Christophe Eloy, CEO of Yole Developpement; Risto Puhakka, president of VLSI Research; Carolyn Evans, chief economist at Intel; Duncan Meldrum, chief economist at Hilltop Economics; and Rozalia Beica, head of the semiconductor business at AT&S... » read more

Planning For Panel-Level Fan-out
By Mark LaPedus - 21 Nov, 2019 - Comments: 0

Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

Embedded Die Packaging Emerges
By Mark LaPedus - 09 Apr, 2018 - Comments: 1

Embedded die packaging is seeing renewed demand amid the push towards chips and systems that require smaller form factors. ASE, AT&S, GE, Shinko, Taiyo Yuden, TDK, Würth Elektronik and others compete in the merchant embedded die packaging market, according to Yole Développement. In fact, ASE and TDK have a joint venture in the arena, which is beginning to ramp up production. Additional... » read more

Inside Panel-Level Fan-Out Technology
By Mark LaPedus - 11 Sep, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encap... » read more

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