Week In Review: Manufacturing, Test

By Mark LaPedus - 08 Oct, 2021 - Comments: 0

Government policy Hoping to resolve the ongoing worldwide chip shortage situation, the U.S. Department of Commerce late last month launched a “request for information (RFI)” initiative, which involved sending questionnaires to various semiconductor companies. The U.S. government is asking all parts of the supply chain – producers, consumers, and intermediaries – to voluntarily share in... » read more

The Week In Review: Design/IoT

By Jesse Allen - 10 Jul, 2015 - Comments: 0

The EDA Consortium announced EDA industry revenue increased 7.5% for Q1 2015 to $1877 million, compared to $1746.1 million in Q1 2014. The four-quarters moving average, which compares the most recent four quarters to the prior four quarters, increased by 8.0%. Employment also increased, and according to Wally Rhines, "all categories showed revenue increases except CAE. Geographically, the Ameri... » read more

Blog Review: March 18

By Jesse Allen - 18 Mar, 2015 - Comments: 0

How do you quantify effort spent in FPGA verification? Mentor's Harry Foster tackles the question in his latest installment of the Wilson Research Group functional verification study. A new frontier of design challenges is rapidly emerging, according to ARM CEO Simon Segars. Cadence's Brian Fuller brings us his keynote address at CDNLive. Synopsys' Tushar Mattu is back with more on AXI VI... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: BBC

Week In Review: Manufacturing, Test

The Week In Review: Design/IoT

Blog Review: March 18

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Knowledge Centers
Entities, people and technologies explored