Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)


A new technical paper titled "RISC-H: Rowhammer Attacks on RISC-V" was published by researchers at ETH Zurich.  RISC-H will be presented at DRAMSec (co-located with ISCA 2024) Abstract: "The first high-end RISC-V CPU with DDR4 support has been released just a few months ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear whether it is possible to compromise ... » read more

A Novel Approach To Mitigating RowHammer Attacks And Improving Server Memory System Reliability


A technical paper titled “RAMPART: RowHammer Mitigation and Repair for Server Memory Systems” was published by researchers at Rambus. Abstract: "RowHammer attacks are a growing security and reliability concern for DRAMs and computer systems as they can induce many bit errors that overwhelm error detection and correction capabilities. System-level solutions are needed as process technology... » read more

Similar But Different — The Tale Of Transient And Permanent Faults


When determining whether an IC is safe from random hardware faults, applying safety metrics such as PMHF, SPFM, and LFM, engineers must analyze both transient and permanent faults. This paper highlights the fundamental differences between permanent and transient faults on digital circuits, and why this distinction is important in the context of the ISO 26262:2018 functional safety standard. ... » read more