tag: Brewer Science

Increasing Roles For Robotics In Fabs
By Gregory Haley - 19 Aug, 2024 - Comments: 0

Different types of robots with greater precision and mobility are beginning to be deployed in semiconductor manufacturing, where they are proving both reliable and cost-efficient. Static robots have been used for years inside of fabs, but they now are being supplemented by collaborative robots (cobots), autonomous mobile robots (AMRs), and autonomous humanoid robots to meet growing and widen... » read more

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System
By Jessica Albright - 15 Aug, 2024 - Comments: 0

High-bandwidth memory blocks (HBM), microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yield, whi... » read more

Chip Industry Week in Review
By The SE Staff - 02 Aug, 2024 - Comments: 0

Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Key Technologies To Extend EUV To 14 Angstroms
By Laura Peters - 29 Jul, 2024 - Comments: 3

The top three foundries plan to implement high-NA EUV lithography as early as 2025 for the 18 angstrom generation, but the replacement of single exposure high-NA (0.55) over double patterning with standard EUV (NA = 0.33) depends on whether it provides better results at a reasonable cost per wafer. So far, 2024 has been a banner year for high-numerical aperture EUV lithography. Intel Foundry... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding
By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

Chip Industry Week In Review
By The SE Staff - 03 Jul, 2024 - Comments: 0

Early version due to U.S. holiday. The U.S. government announced a new $504 million funding round for 12 Regional Technology and Innovation Hubs (Tech Hubs) for semiconductors, clean energy, biotechnology, AI, quantum computing, and more. Among the recipients: NY SMART I-Corridor Tech Hub (New York): $40 million for semiconductor manufacturing; Headwaters Hub (Montana): $41 million f... » read more

Exploring The Fundamentals Of Photolithography
By Joyce Lowes - 23 May, 2024 - Comments: 0

In the semiconductor materials industry, photolithography is a crucial technology for creating intricate electronic circuits. Essentially, it’s the art of printing at the nanoscale level, enabling the precise patterning of semiconductor materials. The ability to do this well is important for companies in the industry because it determines how detailed and efficient microchips can be. This aff... » read more

Reducing Risk In The Semiconductor Supply Chain
By Laura Peters - 23 May, 2024 - Comments: 0

Companies that were hit with chip shortages during the pandemic are changing their strategies to prevent future problems, deploying a combination of supply chain mapping, second sourcing, and digital transformation. Those shortages caused a $200 billion loss for automotive manufacturers, and the disruptions were far more widespread, in many cases lasting for years. Companies of all sorts wer... » read more

What Works Best For Chiplets
By Anne Meixner - 18 Apr, 2024 - Comments: 0

The semiconductor industry is preparing for the migration from proprietary chiplet-based systems to a more open chiplet ecosystem, in which chiplets fabricated by different companies of various technologies and device nodes can be integrated in a single package with acceptable yield. To make this work as expected, the chip industry will have to solve a variety of well-documented technical an... » read more

Backside Power Delivery Gears Up For 2nm Devices
By Laura Peters - 26 Feb, 2024 - Comments: 1

The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more

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