Process Innovations Enabling Next-Gen SoCs and Memories


Achieving improvements in performance in advanced SoCs and packages — those used in mobile applications, data centers, and AI — will require complex and potentially costly changes in architectures, materials, and core manufacturing processes. Among the options under consideration are new compute architectures, different materials, including thinner barrier layers and those with higher th... » read more

Managing Thermal-Induced Stress In Chips


At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

Week In Review: Semiconductor Manufacturing, Test


Chips for consumer devices are down, but the overall chip industry is actively preparing for the next phase of growth. Worldwide silicon wafer shipments, which are an aggregate view of all the various semiconductor segments, hit an all-time high in 2022, increasing 4% to 14,713 million square inches (MSI). Wafer revenue, meanwhile, rose 9.5% to $13.8 billion over the same period, SEMI reported ... » read more

The Path To Known Good Interconnects


Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

The March Toward Chiplets


The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

Week In Review: Semiconductor Manufacturing, Test


Nikkei Asia reports the U.S. is urging allies, including Japan, to restrict exports of advanced semiconductors and related technology to China. The U.S. holds 12% of the global semiconductor market, Japan has a 15% share, while Taiwan and South Korea each have about a 20% share. Some U.S. companies have called for other countries to adopt U.S.-style export curbs, arguing it is unfair for only A... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Ford Motor Company revealed it lost $827 million in the third quarter because of parts shortages and unexpected supplier costs. Those shortages affected 40,000 to 50,000 vehicles. The company is shutting down its interest in its self-driving car unit Argo.ai, which it shared with Volkswagen since 2019. Ford will instead focus on advanced driver-assist systems (ADAS), which... » read more

Which Foundry Is In The Lead? It Depends.


The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures


Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter... » read more

Realization Of Sub-30-Pitch EUV Lithography Through The Application Of Functional Spin-On Glass


Photoresist metrics such as resolution, roughness, CD uniformity, and overall process window are often aimed to realize the full potential of EUV lithography. From the view of the materials supplier, improvements over the aforementioned metrics can be achieved by optimizing the functional materials used under the resist. The underlayers can significantly enhance the resist performance by provid... » read more

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