Chip Industry Week In Review


Breaking news: Nvidia and Synopsys announced a multi-faceted, multi-year deal that includes everything from digital twins to CUDA programming, engineering, and marketing collaboration, and Nvidia's $2B purchase of Synopsys stock. [Updated 12/1] Memory news: Micron is building a $9.6B HBM facility in the city of Higashi-Hiroshima Japan, reports Nikkei. China's ChangXin Memory Technol... » read more

New Panel Production Efforts Target Interposer Costs


The rising cost of increasingly large interposers is spurring renewed interest in panel-level manufacturing, which for years has hobbled along due to the massive and collective effort required by the chip industry to change formats. Several companies are developing their own processes, although there is currently no commercial production. And a new consortium called Joint3, spearheaded by Ja... » read more

The Thermal Trap: How Dielectrics Limit Device Performance


The spread of artificial intelligence is forcing an uncomfortable truth on semiconductor manufacturing. Thin films, which are essential for isolating signals and insulating different components and metal layers, are becoming heat traps as physical dimensions continue to shrink in chips used inside AI data centers. That, in turn, is limiting how fast these chips can process data and increasing t... » read more

Ensuring Reliability Becomes Harder In Multi-Die Assemblies


Multi-die assemblies are bringing together a variety of materials and processes with distinctly different physical properties, creating significant challenges in manufacturing and packaging that can impact yield at time zero and reliability in the field. What passes electrical screening at the end of the line may look good on paper, but these devices can still fail once exposed to rapid and ... » read more

Chip Industry Week In Review


U.S. Trade Representative Jamieson Greer warned Southeast Asian semiconductor manufacturers that they must shift production to the U.S. or face new punitive tariffs, reports the South China Morning Post. President Trump previously floated a 100% tariff on imported chips. Malaysia and other regional economies are offering large concessions and promises of U.S. goods purchases in hopes of securin... » read more

Mitigating Warpage In Multi-Chiplet Systems


Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

Precision Under Pressure: Managing Materials Complexity In Advanced Packaging


In the race to extend Moore's Law through advanced packaging, the limits of precision are no longer defined solely by lithography. Increasingly, they are dictated by the unpredictable behavior of materials. Semiconductor packaging today is no longer limited to just silicon and copper. It includes an expanding range of polymers, adhesives, dielectrics, exotic metals, along with substrates suc... » read more

Chip Industry Week in Review


Cadence plans to buy Hexagon AB's design and engineering business to accelerate expansion in physical AI and system design and analysis. Cadence will pay ~US$3.1 billion in cash and issue stock, with the deal expected to close in early 2026. PWC issued a 104-page in-depth analysis of semiconductor technology and markets, highlighting a broad swath of changes: $1T in annual revenue by 2030, ... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Manufacturing At The Limits


Hybrid bonding has been in production for several years, with mature flows capable of delivering robust yields using 10µm interconnects. At that scale, processes can tolerate hundreds of nanometers of overlay variation, modest differences in wafer bow, and particle sizes rivaling the interconnect height without catastrophic impact. Hybrid bonding is compatible with optical metrology, existing ... » read more

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