tag: Brewer Science

Back-End Packaging And Test: From Lessons Learned To Future Innovations
By Jessica Albright - 20 Feb, 2025 - Comments: 0

The semiconductor industry is a hallmark of technological innovation, evolving rapidly to meet the demands of an increasingly digital world. At its core, semiconductor manufacturing involves two main stages: front-end processes, (wafer fabrication) and back-end processes (packaging and test). Wafer fabrication consists of creating microscopic electronic circuits on a silicon wafer. Packaging an... » read more

EUV’s Future Looks Even Brighter
By Gregory Haley - 20 Feb, 2025 - Comments: 1

The rapidly increasing demand for advanced-node chips to support everything-AI is putting pressure on the industry's ability to meet demand. The need for cutting-edge semiconductors is accelerating in applications ranging from hyperscale data centers powering large language models to edge AI in smartphones, IoT devices, and autonomous systems. But manufacturing those chips relies heavily on ... » read more

Electrifying Everything: Power Moves Toward ICs
By Gregory Haley - 23 Jan, 2025 - Comments: 0

As electronic systems grow increasingly complex and energy-intensive, traditional power management methods — centered on centralized systems and external components — are proving inadequate. The next wave of innovation is to bring power control closer to the action — directly on the chip or into a heterogeneous package. This change is driven by a relentless pursuit of efficiency, scala... » read more

Upcoming Challenges And Changes In Semiconductor Materials
By Laura Peters And Ed Sperling - 23 Jan, 2025 - Comments: 0

Semiconductor Engineering sat down with Dan Brewer and Srikanth Kommu, co-CEOs at Brewer Science, to talk about current and future changes in materials used in semiconductor manufacturing and adjacent markets. What follows are excerpts of that conversation. SE: What was behind the decision to have co-CEOs instead of just one? Brewer: We see a lot of value to having multiple perspectives b... » read more

Baby Steps Toward 3D DRAM
By Bryon Moyer - 17 Dec, 2024 - Comments: 0

Flash memory has made incredible capacity strides thanks to monolithic 3D processing enabled by the stacking of more than 200 layers, which is on its way to 1.000 layers in future generations.[1] But the equally important DRAM has achieved a similar manufacturable 3D architecture. The need for a sufficiently large means of storing charge — such as a capacitor — has proved elusive. Severa... » read more

Navigating Increased Complexity In Advanced Packaging
By Gregory Haley - 17 Dec, 2024 - Comments: 1

As chips evolve toward stacked, heterogeneous assemblies and adopt more complex materials, engineers are grappling with new and often less predictable sources of variation. This is redefining what it means to achieve precision, forcing companies to rethink everything from process control and in-line metrology to materials selection and multi-level testing. These assemblies are the result of ... » read more

NAND Flash Targets 1,000 Layers
By Bryon Moyer - 04 Dec, 2024 - Comments: 0

The chip industry is pushing to quadruple the stack height of 3D NAND flash from 200 layers to 800 layers or more over the next few years, using the additional capacity will help to feed the unending need for more memory of all types. Those additional layers will add new reliability issues a number of incremental reliability challenges, but the NAND flash industry has been steadily increasin... » read more

FOPLP Gains Traction in Advanced Semiconductor Packaging
By Gregory Haley - 21 Nov, 2024 - Comments: 1

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency. Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ab... » read more

New Tradeoffs In Leading-Edge Chip Design
By Katherine Derbyshire - 21 Nov, 2024 - Comments: 0

Device design begins with the anticipated workload. What is it actually supposed to do? What resources — computational units, memory, sensors — are available? Answering these questions and developing the functional architecture are the first steps in a new design — well before committing it to silicon, said Tim Kogel, senior director of technical product management at Synopsys. Yet eve... » read more

Hybrid Bonding Makes Strides Toward Manufacturability
By Laura Peters - 28 Oct, 2024 - Comments: 0

Hybrid bonding is gaining traction in advanced packaging because it offers the shortest vertical connection between dies of similar or different functionalities, as well as better thermal, electrical and reliability results. Advantages include interconnect scaling to submicron pitches, high bandwidth, enhanced power efficiency, and better scaling relative to solder ball connections. But whil... » read more

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