Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Characterizing Defects Inside Hexagonal Boron Nitride (KAIST, NYU, et al.)


A new technical paper titled "Characterizing Defects Inside Hexagonal Boron Nitride Using Random Telegraph Signals in van der Waals 2D Transistors" was published by researchers at KAIST, NYU, Brookhaven National Laboratory, and National Institute for Materials Science. Abstract: "Single-crystal hexagonal boron nitride (hBN) is used extensively in many two-dimensional electronic and quantu... » read more

Research Bits: Feb. 19


DNA assembly of 3D nanomaterials Scientists from Brookhaven National Laboratory, Columbia University, and Stony Brook University developed a method that uses DNA to instruct molecules to organize themselves into targeted 3D patterns and produce a wide variety of designed metallic and semiconductor 3D nanostructures. “We have been using DNA to program nanoscale materials for more than a de... » read more

Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Hacking DNA To Make 3D Nanostructures


A technical paper titled “Three-dimensional nanoscale metal, metal oxide, and semiconductor frameworks through DNA-programmable assembly and templating” was published by researchers at Brookhaven National Laboratory, Columbia University, and Stony Brook University. Abstract: "Controlling the three-dimensional (3D) nanoarchitecture of inorganic materials is imperative for enabling their no... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

Chip Industry Technical Paper Roundup: Dec 18


New technical papers added to Semiconductor Engineering’s library this week. [table id=176 /] More ReadingTechnical Paper Library home » read more

2D Computing Magnets For Temperatures Up To 170-Degrees Fahrenheit


A technical paper titled “Magnetic properties of intercalated quasi-2D Fe3-xGeTe2 van der Waals magnet” was published by researchers at University of Texas at El Paso, National Institute of Standards and Technology (NIST), University of Edinburgh, Donostia International Physics Centre (DIPC), Hampton University, and Brookhaven National Laboratory. Abstract: "Among several well-kno... » read more

Technical Paper Roundup: November 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=167 /] More Reading Technical Paper Library home » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

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