ANN Framework for Thermal-Aware Modeling of GAAFETs (NYCU)


A new technical paper, "A Device-Physics-Informed Artificial Neural Network Approach for Thermal-Aware I-V and C-V Modeling of GAA FETs," was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work introduces a device-physics-informed neural network framework for simultaneous modeling of thermal-aware I-V and C-V characteristics of gate-all-around (GAA) f... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs


A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Week In Review: Design, Low Power


Cadence unveiled a static timing/signal integrity analysis and power integrity analysis tool, Tempus Power Integrity Solution, that integrates the Tempus Timing Signoff and Voltus IC Power Integrity signoff engines. Early use cases demonstrated it correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%. Arasan... » read more