Week In Review: Design, Low Power

Static timing & signal integrity analysis; MIPI D-PHY IP; BSIM-CMG FinFET; Ansys, Rambus Q3.


Cadence unveiled a static timing/signal integrity analysis and power integrity analysis tool, Tempus Power Integrity Solution, that integrates the Tempus Timing Signoff and Voltus IC Power Integrity signoff engines. Early use cases demonstrated it correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%.

Arasan Chip Systems launched MIPI D-PHY IP supporting the D-PHY v2.1 specification for speeds up to 4500 Mbps. The IP is available as standard Tx / Rx pair or as Tx only or Rx only, and is targeted at camera sensor applications in the high end mobile and automobile SoCs.

The Si2 Compact Model Coalition published the latest version of BSIM-CMG FinFET, a standard compact SPICE model developed by researchers at the University of California, Berkeley along with industry partners. CMC chair Peter Lee said, “It has been two-and-a-half years since the last major BSIM-CMG update, which is equivalent to a semiconductor generation or two. This new version implements 25 enhancements and 13 bug fixes which improve accuracy, convergence, and performance when compared to the previous version.” Enhancements to release 111.0.0 include improvements to the thermal noise model and the introduction of gate current scaling factors. Bug fixes include corrected parameter range, and use of macros instead “ifdef’s”.

Samsung adopted Synopsys’ VC LP tool for low-power signoff and static verification of large-scale, complex SoCs. VC LP includes the Signoff Abstract Model (SAM) based methodology, which Samsung said provided up to 5X performance gains and up to 6X less memory footprint with the same quality of results and debug visibility compared to flat run methods for low-power signoff.

Ansys teamed up with Microsoft on compute integration and digital twin definition language to allow manufacturers that model and connect assets using Azure Digital Twins to optimize asset production and operations using ANSYS Twin Builder.

Rambus reported third quarter 2019 financial results with revenue of $57.4 million, down 4% from $59.8 million in the same period last year but exceeding expectations for the quarter. On a GAAP basis, Q3 2019 had a loss per share of $0.16, up from a net loss per share of $0.97 in Q3 2018. During the quarter, Rambus sold its payments and ticketing business to Visa while refocusing on semiconductor with the acquisitions of Northwest Logic and Verimatrix’s IP business (formerly Inside Secure).

Ansys reported third quarter 2019 financial results with revenue of $343.9, up 19% from the same quarter last year. On a GAAP basis, earnings per share for Q3 2019 stood at $1.04, unchanged from Q3 2018. Non-GAAP earnings per share were $1.42, up 8% from $1.31 in the same quarter last year. This quarter Ansys also closed the acquisitions of Livermore Software Technology Corporation for $779.9 million and Dynardo for approximately €30.0 million (~$33.3 million). The company raised revenue expectations for the year.

Check out upcoming industry events and conferences: The ESD Alliance will host a program during SEMICON Europa in Munich, Germany, on November 13 featuring a series of presentations and a panel discussion highlighting how advances in electronic system design are enabling emerging and future applications. Accellera will hold a Proposed Working Group meeting on a potential standard for FMEDA tool interoperability on Dec. 6 at NXP in Munich, Germany. The RISC-V Summit will include talks, an expo, and tutorials on the open ISA Dec. 10-12 in San Jose, CA.

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