tag: Cadence Design Systems

Toward Domain-Specific EDA
By Brian Bailey - 26 Sep, 2022 - Comments: 0

More companies appear to be creating custom EDA tools, but it is not clear if this trend is accelerating and what it means for the mainstream EDA industry. Whenever there is change, there is opportunity. Change can come from new abstractions, new options for optimization, or new limitations that are imposed on a tool or flow. For example, the slowing of Moore's Law means that sufficient prog... » read more

Strengthening The Global Semi Supply Chain
By Ann Mutschler - 22 Sep, 2022 - Comments: 0

Within the semiconductor ecosystem, there are a number of dynamics pointing to the need for new ways of partnering in more meaningful ways that bring resiliency to the global semiconductor supply chain. One of these is the move to bespoke silicon, stemming from a shift in the companies that create most SoCs today -- the hyperscalar cloud providers. These market leaders know their workloads so w... » read more

Efficient Verification Of Mixed-Signal Series IP Using UVM
By Cadence - 21 Sep, 2022 - Comments: 0

Interface IP are an integral part of systems-on-chips (SoC) that include mobile, automotive, or networking applications and are primarily used for transmitting data over a physical medium between a host and device. The mixed-signal nature of the IP makes verification a challenging task, requiring special considerations for digital and analog sections. This paper describes a robust mixed-signal ... » read more

How Mature Are Verification Methodologies?
By Brian Bailey - 14 Sep, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss differences between hardware and software verification and changes and challenges facing the chip industry, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president o... » read more

Designing For Thermal
By Karen Heyman - 13 Sep, 2022 - Comments: 0

Heat has emerged as a major concern for semiconductors in every form factor, from digital watches to data centers, and it is becoming more of a problem at advanced nodes and in advanced packages where that heat is especially difficult to dissipate. Temperatures at the base of finFETs and GAA FETs can differ from those at the top of the transistor structures. They also can vary depending on h... » read more

Preparation Of Geometry Models For Mesh Generation And CFD
By Cadence - 12 Sep, 2022 - Comments: 0

Making geometry models suitable for CFD meshing is a time-consuming bottleneck in CFD analysis. We will discuss why and ways to fix the problems. Click here to read more. » read more

Week In Review: Auto, Security, Pervasive Computing
By Susan Rambo - 26 Aug, 2022 - Comments: 0

Automotive, mobility California will ban the sale of new gasoline vehicles so that by 2035 100% of new cars and light trucks sold in California will be zero-emission vehicles. NXP Semiconductors announced multi-year supply agreements for its S32 family. Agreements to supply the S32 domain and zonal automotive processors to OEMs will include upcoming 5nm ASIL-D processors. Keysight Techno... » read more

How Climate Change Affects Data Centers
By Marie C. Baca - 25 Aug, 2022 - Comments: 0

Data centers are hot, and they may get even hotter. As climate change impacts temperatures around the world, designers are changing the computing hubs that are tied to nearly every aspect of modern life to make them more efficient, more customized, and potentially more disaggregated. These shifts are taking on new urgency as the tech industry grapples with months of sweltering temperatures o... » read more

Verification Scorecard: How Well Is The Industry Doing?
By Brian Bailey - 25 Aug, 2022 - Comments: 0

Semiconductor Engineering sat down to discuss how well verification tools and methodologies have been keeping up with demand, with Larry Lapides, vice president of sales for Imperas Software; Mike Thompson, director of engineering for the verification task group at OpenHW; Paul Graykowski, technical marketing manager for Arteris IP; Shantanu Ganguly, vice president of product marketing at Caden... » read more

Is There A Limit To The Number of Layers In 3D-NAND?
By Karen Heyman - 24 Aug, 2022 - Comments: 1

Memory vendors are racing to add more layers to 3D NAND, a competitive market driven by the explosion in data and the need for higher-capacity solid state drives and faster access time. Micron already is filling orders for 232-layer NAND, and not to be outdone, SK Hynix announced that it will begin volume manufacturing 238-layer 512Gb triple level cell (TLC) 4D NAND in the first half of next... » read more

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