tag: Cadence

System-Driven PPA For Multi-Chiplet Designs
By Cadence - 20 Dec, 2023 - Comments: 0

As we approach the device scaling limitations at advanced nodes, the demand on compute performance and data transfer for hyperscale data center and AI designs is at an all-time high. Advanced systems-on-chip (SoCs) are reaching reticle size limits, and there has been a need to find innovative solutions to continue Moore’s law scaling and achieve performance improvements with reduced power. St... » read more

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2023 - Comments: 0

Siemens' Huw Geddes finds that the flexibility offered by the RISC-V ISA can introduce further verification and validation requirements to ensure that the combination of extensions and customization not just works but does not break anything else while delivering expected performance, plus looks at how processor trace can help. Cadence's Gustavo Araujo explains the various optimizations in t... » read more

Chip Industry Week In Review
By The SE Staff - 15 Dec, 2023 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

Using Real Workloads To Assess Thermal Impacts
By Ann Mutschler - 14 Dec, 2023 - Comments: 0

Thermal analysis is being driven much further left in the design, fueled by demand for increased transistor density and more features on a chip or in a package, as well as the unique ways the various components may be exercised or stressed. However, getting a clear picture of the thermal activity in advanced-node chips and packages is extremely complex, and it can vary significantly by use c... » read more

Data Formats For Inference On The Edge
By Brian Bailey - 14 Dec, 2023 - Comments: 0

AI/ML training traditionally has been performed using floating point data formats, primarily because that is what was available. But this usually isn't a viable option for inference on the edge, where more compact data formats are needed to reduce area and power. Compact data formats use less space, which is important in edge devices, but the bigger concern is the power needed to move around... » read more

Decoding GDS To Thermal Model Conversion
By Jasmine Jasmine - 14 Dec, 2023 - Comments: 0

Driven by Moore’s Law and modern, ubiquitous computation power demand, the market will continue to demand higher chip performance. Therefore, modern chips with ever-higher power densities present critical thermal challenges. With the ever-shrinking design margins, designers must manage their thermal budget at every stage of the design, from chip to system. Now, let us shift left and start ... » read more

Demystifying Mixed-Signal Simulation For Digital Verification Engineers
By Cadence - 13 Dec, 2023 - Comments: 0

The convergence of analog and digital technologies on a single chip, commonly referred to as mixed-signal, has reshaped the integrated circuit (IC) landscape. In recent years, mixed-signal designs have emerged as the dominant technology, therefore requiring traditional analog and digital methodologies to be enhanced. A mixed-signal design offers many advantages, including boosted performance, r... » read more

Blog Review: December 13
By Jesse Allen - 13 Dec, 2023 - Comments: 0

Synopsys' Charles Dittmer discusses key and emerging use cases for Bluetooth Low Energy and how combining BLE with other wireless protocols can open new avenues of functionality for application areas including automotive, hearables, and retail. Cadence's Neelabh Singh points out changes in the terminologies describing USB4 links and shows the various possible link configurations put forth by... » read more

Chip Industry Week In Review
By The SE Staff - 08 Dec, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Security Becoming Core Part Of Chip Design — Finally
By Ann Mutschler - 07 Dec, 2023 - Comments: 1

Security is shifting both left and right in the design flow as chipmakers wrestle with how to build devices that are both secure by design and resilient enough to remain secure throughout their lifetimes. As increasingly complex devices are connected to the internet and to each other, IP vendors, chipmakers, and systems companies are racing to address existing and potential threats across a ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy