Blog Review: Jan. 22

By Ed Sperling - 22 Jan, 2014 - Comments: 0

Mentor’s Anil Khanna believes Nest’s approach should be incorporated into the entire power grid. The ramifications of that are interesting to ponder. Speaking of Nest, Cadence’s Brian Fuller looks at the implications of the $3.2 billion acquisition of the company by Google. Will Google get it right? Maybe. Synopsys’ Richard Solomon has come up with a new definition for New Year’... » read more

Power’s Impact On Hierarchy Modification

By Ann Mutschler - 16 Jan, 2014 - Comments: 2

RTL restructuring in which the logical hierarchy of a design is modified is usually done to manage complex designs. When power management is added to this task, new challenges crop up. Consider switchable power or voltage domains, which are a common way to manage power is to use switchable power or voltage domains. When implementing this technique, all the logic in such a domain must hang of... » read more

Verifying Power Optimized Designs Using Sequential Analysis

By Rob Eccles - 16 Jan, 2014 - Comments: 0

All power optimization tools can perform combinational optimization, where there is an opportunity to gate a register clock input, based on the combinational logic that is feeding the register’s data input. While this method works well and does not alter the logic behavior at the register, the problem is that it leaves additional power saving opportunities on the table. However, sequential... » read more

Blog Review: Dec. 11

By Ed Sperling - 11 Dec, 2013 - Comments: 0

Synopsys’ Brent Gregory has developed a career growth checklist for computer science majors. They should hang this in the hallway at universities. Cadence’s Brian Fuller interviews Saar Drimer, a UK hardware engineer who has been experimenting with odd-shaped PCBs. According to Drimer, 45-degree angles aren’t always optimal. But what happens to all the expensive tools everyone has bee... » read more

What’s Next For Power Optimization

By Brian Bailey - 05 Dec, 2013 - Comments: 1

Today it is difficult to find a design that does not consider some kind of power optimization. Mobile needs it to preserve battery life, data centers need it to reduce operating cost, and many are finding they need it to meet tougher regulatory requirements. In a survey conducted two years ago, there was no segment of the industry that was not taking a serious look at reducing their power profi... » read more

New Challenges Emerge With FinFETs

By Ed Sperling - 05 Dec, 2013 - Comments: 0

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Early reports ... » read more

Power Optimization Considered

By Abhishek Ranjan - 05 Dec, 2013 - Comments: 0

The explosive emergence of hand-held computing and entertainment devices fuels an ever-increasing demand for longer battery life. In fact, 70% of all new hardware development is targeted toward mobile devices. Ancillary to this phenomenon, technology scaling has increased the number of transistors that can be packed per unit area. More and more functionality can be put into electronic devices. ... » read more

Lightening The Information Overload

By Abhishek Ranjan - 22 Nov, 2013 - Comments: 0

We live in an age where it’s very easy to suffer from information overload — even when that information leads to better designs. Power optimization tools have been very well received in the market, with almost every major electronics company using these tools and seeing the benefits. Yet, if a power optimization tool shows you everything you can do to improve your design, it’s too much... » read more

Paving The Way To 16/14nm

By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

Will History Repeat Itself?

By Brian Bailey - 24 Oct, 2013 - Comments: 0

Hands up — how many people read the books by Clayton Christensen, books such as The Innovator’s Dilemma? His books were talked about endlessly in the corridors of the EDA companies when they first came out. They all wanted to identify the next disruption and could find reasons why almost every new tool was going to be disruptive. For people not familiar with his work, his main premise wa... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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