Building CFETs With Monolithic And Sequential 3D

By Katherine Derbyshire - 22 Feb, 2024 - Comments: 0

Successive versions of vertical transistors are emerging as the likely successor to finFETs, combining lower leakage with significant area reduction. A stacked nanosheet transistor, introduced at N3, uses multiple channel layers to maintain the overall channel length and necessary drive current while continuing to reduce the standard cell footprint. The follow-on technology, the CFET, pushes... » read more

Chip Industry Technical Paper Roundup: Feb. 13

By Liz Allan - 13 Feb, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=197 /] More ReadingTechnical Paper Library home » read more

Benchmarking Electron Holography And Pixelated STEM On Various Semiconductor Structures

By Technical Paper Link - 06 Feb, 2024 - Comments: 0

A technical paper titled “Measuring electrical properties in semiconductor devices by pixelated STEM and off-axis electron holography (or convergent beams vs. plane waves).” was published by researchers at CEA-LETI at the Universite Grenoble Alpes and EPFL. Abstract: "We demonstrate the use of both pixelated differential phase contrast (DPC) scanning transmission electron microscopy (STEM... » read more

Research Bits: Jan. 23

By Jesse Allen - 23 Jan, 2024 - Comments: 0

Memristor-based Bayesian neural network Researchers from CEA-Leti, CEA-List, and CNRS built a complete memristor-based Bayesian neural network implementation for classifying types of arrhythmia recordings with precise aleatoric and epistemic uncertainty. While Bayesian neural networks are useful for at sensory processing applications based on a small amount of noisy input data because they ... » read more

Chip Industry Technical Paper Roundup: Jan. 23

By Liz Allan - 23 Jan, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=189 /] More ReadingTechnical Paper Library home » read more

3D Integration Supports CIM Versatility And Accuracy

By Katherine Derbyshire - 18 Jan, 2024 - Comments: 0

Compute-in-memory (CIM) is gaining attention due to its efficiency in limiting the movement of massive volumes of data, but it's not perfect. CIM modules can help reduce the cost of computation for AI workloads, and they can learn from the highly efficient approaches taken by biological brains. When it comes to versatility, scalability, and accuracy, however, significant tradeoffs are requir... » read more

Novel Neuromorphic Artificial Neural Network Circuit Architecture

By Technical Paper Link - 15 Jan, 2024 - Comments: 0

A technical paper titled “Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems” was published by researchers at CEA-LETI Université Grenoble Alpes, University of Zurich and ETH Zurich. Abstract: "The brain’s connectivity is locally dense and globally sparse, forming a small-world graph—a principle prevalent in the evolution of various species, sugg... » read more

Money Pours Into New Fabs And Facilities

By Liz Allan - 03 Jan, 2024 - Comments: 0

Fabs, packaging, test and assembly, and R&D all drew major funding in 2023. Companies poured money into offshore locations, such as India and Malaysia, to access a larger workforce and lower costs, while also partnering with governments to secure domestic supply chains amid ongoing geopolitical turmoil. Looking ahead, artificial intelligence (AI), quantum computing, and data applications... » read more

Chip Industry Week In Review

By The SE Staff - 22 Dec, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan More than 1 billion generative AI smartphones are expected be shipped during 2024 to 2027, reports Counterpoint. The share of GenAI smartphones will be 4% of the market in 2023 and is likely to double in 2024, with Samsung capturing half the market, followed by Chinese OEMs. By 2027, GenAI smartphones could account for 40% of the market. Global ... » read more

Modeling Compute In Memory With Biological Efficiency

By Katherine Derbyshire - 19 Dec, 2023 - Comments: 0

The growing popularity of generative AI, which uses natural language to help users make sense of unstructured data, is forcing sweeping changes in how compute resources are designed and deployed. In a panel discussion on artificial intelligence at last week’s IEEE Electron Device Meeting, IBM’s Nicole Saulnier described it as a major breakthrough that should allow AI tools to assist huma... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

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by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.