tag: CEA-Leti

Angstrom-Level Measurements With AFMs
By Mark LaPedus - 19 Aug, 2021 - Comments: 0

Competition is heating up in the atomic force microscopy (AFM) market, where several vendors are shipping new AFM systems that address various metrology challenges in packaging, semiconductors and other fields. AFM, a small but growing field that has been under the radar, involves a standalone system that provides surface measurements on structures down to the angstrom level. (1 angstrom = 0... » read more

Manufacturing Bits: July 13
By Mark LaPedus - 13 Jul, 2021 - Comments: 0

Heterogenous III-V packaging At the recent 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), a group presented a paper on the development of a wafer-level fan-out package using heterogenous III-V devices. This paper deals with the packaging of two III-V chips for use in RF transceiver applications in base stations. III-V Lab, CEA-Leti, Thales and United Monolithic Semic... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Jun, 2021 - Comments: 0

Rambus is making a push for Compute Express Link (CXL) with two acquisitions and the launch of its CXL Memory Interconnect Initiative. The initiative aims to define and develop semiconductor solutions for advanced data center architectures, with initial research and development focusing on solutions to support key memory expansion and pooling use cases. CXL is an open interconnect specificat... » read more

Manufacturing Bits: April 27
By Mark LaPedus - 27 Apr, 2021 - Comments: 0

Next-gen neuromorphic computing The European Union (EU) has launched a new project to develop next-generation devices for neuromorphic computing systems. The project, called MeM-Scales, plans to develop a novel class of algorithms, devices, and circuits that reproduce multi-timescale processing of biological neural systems. The results will be used to build neuromorphic computing systems th... » read more

Manufacturing Bits: Feb. 16
By Mark LaPedus - 16 Feb, 2021 - Comments: 0

Hybrid bonding consortium for packaging A*STAR’s Institute of Microelectronics (IME) and several companies have formed a new consortium to propel the development of hybrid bonding technology for chip-packaging applications. The group, called the Chip-to-Wafer (C2W) Hybrid Bonding Consortium, includes A*STAR’s IME organization, Applied Materials, ASM Pacific, Capcon, HD MicroSystems, ONT... » read more

Week In Review: Manufacturing, Test
By Mark LaPedus - 12 Feb, 2021 - Comments: 0

Chipmakers The U.S. Semiconductor Industry Association (SIA) and several chip executives have sent a joint letter to President Biden, urging the administration to include substantial funding for semiconductor manufacturing and research in the U.S. As reported, the share of global semiconductor manufacturing capacity in the U.S. has decreased from 37% in 1990 to 12% today. “Semiconductors pow... » read more

Week In Review: Design, Low Power
By Jesse Allen - 12 Feb, 2021 - Comments: 0

Renesas Electronics Corporation will acquire Dialog Semiconductor in an all-cash deal worth about US $5.9 billion. Dialog is a supplier of mixed-signal ICs targeting IoT, consumer, automotive, and industrial. The company's primary areas of focus were communications and power control. These products are complementary to existing Renesas embedded compute products. Dialog CEO Dr. Jalal Bagherli... » read more

Manufacturing Bits: Feb. 2
By Mark LaPedus - 02 Feb, 2021 - Comments: 0

Capacitor-less DRAM At the recent 2020 International Electron Devices Meeting (IEDM), Imec presented a paper on a novel capacitor-less DRAM cell architecture. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. DRAM itself is based on a one-transistor, one-capacito... » read more

Manufacturing Bits: Dec. 29
By Mark LaPedus - 29 Dec, 2020 - Comments: 1

Chiplet-based exascale computers At the recent IEEE International Electron Devices Meeting (IEDM), CEA-Leti presented a paper on a 3D chiplet technology that enables exascale-level computing systems. The United States and other nations are working on exascale supercomputers. Today’s supercomputers are measured in floating point operations per second. The world’s fastest supercomputers c... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Nov, 2020 - Comments: 0

Tools Mentor unveiled Tessent Streaming Scan Network software for its Tessent TestKompress software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources for a simplified bottom-up DFT flow. The bus-based scan data distribution architecture enables simultaneous testing of any number of cores and ... » read more

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