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Manufacturing Bits: July 13

Heterogenous III-V packaging; SiP consortium; wafer stacking.

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Heterogenous III-V packaging
At the recent 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), a group presented a paper on the development of a wafer-level fan-out package using heterogenous III-V devices.

This paper deals with the packaging of two III-V chips for use in RF transceiver applications in base stations. III-V Lab, CEA-Leti, Thales and United Monolithic Semiconductors contributed to the work.

Fan-out is a way to assemble one or more dies in an advanced package, enabling chips with better performance and more I/Os for applications like computing, IoT, networking and smartphones. In just one example of fan-out, a DRAM die is stacked on a logic chip in a package. This, in turn, brings the memory and processing functions closer together, providing more bandwidth in systems.

Fan-out can also be used in RF applications like smartphones and base stations. CEA-Leti and others found a way to enable III-V devices in base stations using fan-out.

In this technology, the first die consists of a high-power amplifier (HPA) and a switch based on gallium-nitride (GaN) technology. The GaN device makes use of a silicon carbide (SiC) substrate, sometimes called GaN-on-SiC. The second one features a low-noise amplifier (LNA) and a driver built on gallium arsenide (GaAs).

“Both chips bring together the best of each substrate technology, namely high RF and power performances of GaN, and low-noise capability of GaAs,” said Arnaud Garnier of CEA-Leti and the lead author of the paper.

“The SiP was built using fan-out wafer-level packaging (FOWLP) in chip-first face-down configuration,” Garnier said. “The gap between the chips is as low as 100μm. Electrical routing is secured by redistribution layer (RDL) and balls for flip-chip assembly on the PCB. Thermal dissipation has to be managed opposite to the PCB to avoid a too complex PCB design. It is managed by directly contacting the HPA backside with a Cu-liner acting as a heat spreader.”

This is achieved by opening the molding compound using laser ablation, and subsequently plating copper on the SiP backside. The SiP has a final size of 4- x 4- x 0.35-mm. “Signal losses were measured in an SiP-like environment at 0.1 dB/mm, 0.2 dB/mm and 0.4 dB/mm, respectively, at 30GHz, 40GHz and 60GHz,” Garnier said.

SiP consortium
A*STAR’s Institute of Microelectronics (IME) has announced the formation of a new System-in-Package (SiP) consortium.

The consortium includes Singapore’s IME, Asahi-Kasei, GlobalFoundries, Qorvo and Toray. The goal is to develop advanced packages for 5G applications. A SiP integrates several components into a single package, enabling it to function as an electronic system or subsystem.

Today, carriers are deploying 5G networks at sub-6GHz frequencies. Some carriers are deploying next-generation 5G networks using the mmWave frequency bands at 26GHz, 28GHz and 39GHz.

The industry is developing new IC packages for 5G mmWave. These packages combine an RF chip and the antenna in the same unit, which is called antenna-in-package (AiP). The idea behind these new integrated antenna schemes is to bring the RF chips closer to the antenna to boost the signal and minimize the losses in systems.

There are other challenges as well. “In 5G applications, multiple frequency band operation requires 5G devices to integrate numerous devices, such as filters, low noise amplifiers (LNAs), RF switches and others, to support mobile communication and data-transmission over a range of frequency bands,” according to A*STAR. “3D integration is an ideal way to integrate multiple devices/chiplets inside a small-form factor package.”

IME is teaming with consortium members to apply 3D integration technologies to miniaturize the RF front-end modules for 5G applications.

Wafer stacking
In a separate development, A*STAR’s IME has developed a new technology that could enable next-generation 3D-like chips.

The idea is to process chips on a wafer. Then, the wafers are stacked and bonded using a new wafer bonding technology. Eventually, the dies on one wafer are connected to chips on another wafer.

IME has developed a multi-wafer fusion bonding process and a one-step through-silicon via (TSV) process that can stack up to four layers of wafers. This process can potentially decrease the cost of production by 50%.

IME’s wafer-to-wafer stacking approach makes use of a technology called hybrid bonding. Others are also working on the technology. For this, using a wafer bonder, wafers are bonded using fine-pitch copper-to-copper interconnects. It’s a dielectric-to-dielectric bond, followed by a metal-to-metal connection.

“The 3D integration, TSV process and multi-wafer fusion bonding technology breakthroughs will allow device manufacturers to better integrate 3D products with high added value,” said Kawano Masaya, senior scientist and project lead at A*STAR’s IME.



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