Week In Review: Design, Low Power

By Marie C. Baca - 18 Nov, 2022 - Comments: 0

Tools and IP Cadence announced that its IP for GDDR6 is now silicon-proven for TSMC’s N5 process technology. The IP consists of Cadence PHY, controller design IP, and verification IP (VIP), and is targeted for very high-bandwidth memory applications. “The improved PHY and controller design IP for GDDR6 with DRAM data rates at 22Gbps in the TSMC N5 process is the fastest of the GDDR6 fami... » read more

Repositioning For A Changing IC Market

By Ed Sperling - 26 May, 2022 - Comments: 0

Sailesh Chittipeddi, executive vice president at Renesas, sat down with Semiconductor Engineering to talk about how changes in end markets are shifting demand for technology. What follows are excerpts of that conversation. SE: Renesas has acquired a number of companies over the past several years. What's the goal? Chittipeddi: The goal very simply is to create an industry leading solutio... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 29 Oct, 2021 - Comments: 0

Chipmakers After years in the works, GlobalFoundries is finally a public company. But on its first day of trading on Thursday (Oct. 28), shares of the foundry vendor slipped a bit. GF finished its first day of trading at $46.40. This compares to the $47 per share it priced in the initial public offering (IPO), according a report to Reuters. The chipmaker has a market capitalization of about $2... » read more

January ’19 Startup Funding: $100M+ Rounds Abound

By Jeff Dorsch - 30 Jan, 2019 - Comments: 0

Sixteen companies received private funding rounds of $100 million or more during the month of January, with two privately held companies, Infor and Verily Life Sciences, taking in rounds of $1.5 billion and $1 billion, respectively. The market segments represented in the January rounds were varied. Multiple companies using artificial intelligence technology in their offerings and cloud-based... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Celeno

Week In Review: Design, Low Power

Repositioning For A Changing IC Market

Week In Review: Manufacturing, Test

January ’19 Startup Funding: $100M+ Rounds Abound