Prefetch Side Channels Undermine the Isolation Between User and Kernel Space on AMD CPUs

By Technical Paper Link - 08 Aug, 2022 - Comments: 0

This new technical paper titled "AMD Prefetch Attacks through Power and Time" is from researchers at Graz University of Technology and CISPA Helmholtz Center for Information Security. Note, this is a prepublication paper for the USENIX Security Symposium in Boston in August 2022. This paper includes countermeasures and mitigation strategies, and the paper indicates that the findings were di... » read more

Usability of Authenticity Checks for Hardware Security Tokens

By Technical Paper Link - 08 Sep, 2021 - Comments: 0

Abstract: "The final responsibility to verify whether a newly purchased hardware security token (HST) is authentic and unmodified lies with the end user. However, recently reported attacks on such tokens suggest that users cannot take the security guarantees of their HSTs for granted, even despite widely deployed authenticity checks. We present the first comprehensive market review eva... » read more

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tag: CISPA Helmholtz Center for Information Security

Prefetch Side Channels Undermine the Isolation Between User and Kernel Space on AMD CPUs

Usability of Authenticity Checks for Hardware Security Tokens

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tag: CISPA Helmholtz Center for Information Security

Prefetch Side Channels Undermine the Isolation Between User and Kernel Space on AMD CPUs

Usability of Authenticity Checks for Hardware Security Tokens

Trending Articles

NAND Flash Targets 1,000 Layers

Testing For Thermal Issues Becomes More Difficult

Auto Chip Aging Accelerates In Hot Climates

Is In-Memory Compute Still Alive?

Top-Down Vs. Bottom-Up Chiplet Design

Knowledge Centers Entities, people and technologies explored

Related Articles

Shift Left Is The Tip Of The Iceberg

Partitioning In The Chiplet Era

NAND Flash Targets 1,000 Layers

AI’s Role In Chip Design Widens, Drawing In New Startups

What Comes After HBM For Chiplets

Memory Fundamentals For Engineers

New AI Processors Architectures Balance Speed With Efficiency

Defining The Chiplet Socket

Sponsors

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