Chip Industry Technical Paper Roundup: Oct. 14


New technical papers recently added to Semiconductor Engineering’s library: [table id=367 /] More ReadingTechnical Paper Library home » read more

Lightweight, High-Performance CPU Extension for Protected Key Handles with CPU-Enforced Usage (CISPA, Ruhr Univ. Bochum)


A new technical paper titled "KeyVisor -- A Lightweight ISA Extension for Protected Key Handles with CPU-enforced Usage Policies" was published by researchers at CISPA Helmholtz Center for Information Security and Ruhr University Bochum. Abstract "The confidentiality of cryptographic keys is essential for the security of protection schemes used for communication, file encryption, and outsou... » read more

Chip Industry Technical Paper Roundup: August 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

How Attackers Can Read Data From CPU’s Memory By Analyzing Energy Consumption


A technical paper titled “Collide+Power: Leaking Inaccessible Data with Software-based Power Side Channels” was published by researchers at Graz University of Technology and CISPA Helmholtz Center for Information Security. Abstract: "Differential Power Analysis (DPA) measures single-bit differences between data values used in computer systems by statistical analysis of power traces. In th... » read more

Chip Industry’s Technical Paper Roundup: June 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=105 /] More Reading Technical Paper Library home » read more

Hardware Security: Eliminating/Reducing A Blind Spot of Side Channels (CISPA Helmholtz Center for Information Security)


A technical paper titled "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channels" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract: "In the last years, there has been a rapid increase in microarchitectural attacks, exploiting side effects of various parts of the CPU. Most of them have in common that they rely ... » read more

Chip Industry’s Technical Paper Roundup: Apr. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=94 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us ... » read more

CAN Bus Security Using TDCs (ETH Zurich & CISPA Helmholtz Center)


A technical paper titled "EdgeTDC: On the Security of Time Difference of Arrival Measurements in CAN Bus Systems" was published by researchers at ETH Zurich and CISPA Helmholtz Center for Information Security. Abstract "A Controller Area Network (CAN bus) is a message- based protocol for intra-vehicle communication designed mainly with robustness and safety in mind. In real-world deployment... » read more

Week In Review: Auto, Security, Pervasive Computing


Rambus will begin selling Arm's CryptoCell embedded security platform and CryptoIsland root-of-trust cores, setting the stage for a much broader push by Rambus into security for a wide range of connected devices, and ultimately into security as a service. Under the terms of the deal, Rambus' customers will be able to license Arm IP directly from Rambus. For Arm's existing customers, there will ... » read more

Security Research: Technical Paper Round-Up


A number of hardware security-related technical papers were presented at recent conferences, including the August 2022 USENIX Security Symposium and IEEE’s International Symposium on Hardware Oriented Security and Trust (HOST). Topics include side-channel attacks and defenses (including on-chip mesh interconnect attacks), heterogeneous attacks on cache hierarchies, rowhammer attacks and mitig... » read more

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