Chip Industry’s Technical Paper Roundup: June 5

Quantum computing on chiplets; analog & digital SRAM in-memory computing; LLMs for hardware design; HBM2 DRAM rowhammer issues; 2D material mechanics; ALD-oxide semis; side-channel attacks; 3D memory structures metrology.


New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Compilation for Quantum Computing on Chiplets UC Santa Barbara and Cisco Quantum Lab
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design NYU and University of New South Wales
Inline metrology of high aspect ratio hole tilt and center line shift using small-angle x-ray scattering Bruker Nano and Lam Research
Benchmarking and modeling of analog and digital SRAM in-memory computing
KU Leuven
An Experimental Analysis of RowHammer in HBM2 DRAM Chips ETH Zurich and American University of Beirut
Recent advances in the mechanics of 2D materials McGill University, University of Science and Technology of China, and University of Illinois
Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook Hanyang University
(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channels CISPA Helmholtz Center for Information Security

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