Rowhammer Vulnerability Of A HBM2 DRAM Chip


A new technical paper titled “An Experimental Analysis of RowHammer in HBM2 DRAM Chips” was published by researchers at ETH Zurich and American University of Beirut.


“RowHammer (RH) is a significant and worsening security, safety, and reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it is important to understand real DRAM chips’ RH characteristics. Unfortunately, no prior work extensively studies the RH vulnerability of modern 3D-stacked high-bandwidth memory (HBM) chips, which are commonly used in modern GPUs.

In this work, we experimentally characterize the RH vulnerability of a real HBM2 DRAM chip. We show that 1) different 3D-stacked channels of HBM2 memory exhibit significantly different levels of RH vulnerability (up to 79% difference in bit error rate), 2) the DRAM rows at the end of a DRAM bank (rows with the highest addresses) exhibit significantly fewer RH bitflips than other rows, and 3) a modern HBM2 DRAM chip implements undisclosed RH defenses that are triggered by periodic refresh operations. We describe the implications of our observations on future RH attacks and defenses and discuss future work for understanding RH in 3D-stacked memories.”

Find the technical paper here. Published May 2023 (preprint).

Olgun, Ataberk, Majd Osseiran, Yahya Can Tuğrul, Haocong Luo, Steve Rhyner, Behzad Salami, Juan Gomez Luna, and Onur Mutlu. “An Experimental Analysis of RowHammer in HBM2 DRAM Chips.” arXiv preprint arXiv:2305.17918 (2023).

Leave a Reply

(Note: This name will be displayed publicly)