tag: rowhammer

Analysis Of The On-DRAM-Die Read Disturbance Mitigation Method: Per Row Activation Counting
By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance” was published by researchers at ETH Zürich and TOBB University of Economics and Technology. Abstract: "We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per... » read more

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)
By Technical Paper Link - 13 Jun, 2024 - Comments: 0

A new technical paper titled "RISC-H: Rowhammer Attacks on RISC-V" was published by researchers at ETH Zurich.  RISC-H will be presented at DRAMSec (co-located with ISCA 2024) Abstract: "The first high-end RISC-V CPU with DDR4 support has been released just a few months ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear whether it is possible to compromise ... » read more

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer 
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enh... » read more

Centauri: Practical Rowhammer Fingerprinting Demonstrated On DRAM Modules (UC Davis)
By Technical Paper Link - 30 Apr, 2024 - Comments: 0

A technical paper titled “Centauri: Practical Rowhammer Fingerprinting” was published by researchers at UC Davis. Abstract: "Fingerprinters leverage the heterogeneity in hardware and software configurations to extract a device fingerprint. Fingerprinting countermeasures attempt to normalize these attributes such that they present a uniform fingerprint across different devices or present d... » read more

Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)
By Technical Paper Link - 03 Apr, 2024 - Comments: 0

A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

DRAM Chip Characterization Study of Spatial Variation of Read Disturbance and Future Solutions (ETH Zurich)
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A new technical paper titled "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich. Abstract: "Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used for breaking memory isolation, a fundamental building block for building robust systems. Row... » read more

Securing DRAM Against Evolving Rowhammer Threats
By Aharon Etengoff - 07 Mar, 2024 - Comments: 0

Advanced process nodes and higher silicon densities are heightening DRAM's susceptibility to Rowhammer attacks, as reduced cell spacing significantly decreases the hammer count needed for bit flips. Rowhammer exploits DRAM’s single-capacitor-per-bit design to trigger bit flips in adjacent cells through repeated memory row accesses. This vulnerability allows attackers to manipulate data, re... » read more

Memory’s Future Hinges On Reliability
By Karen Heyman - 14 Feb, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about the impact of power and heat on off-chip memory, and what can be done to optimize performance, with Frank Ferro, group director, product management at Cadence; Steven Woo, fellow and distinguished inventor at Rambus; Jongsin Yun, memory technologist at Siemens EDA; Randy White, memory solutions program manager at Keysight; a... » read more

DRAM Simulator For Evaluation of Memory System Design Changes (ETH Zurich)
By Technical Paper Link - 13 Sep, 2023 - Comments: 0

A technical paper titled “Ramulator 2.0: A Modern, Modular, and Extensible DRAM Simulator” was published by researchers at ETH Zurich. Abstract: "We present Ramulator 2.0, a highly modular and extensible DRAM simulator that enables rapid and agile implementation and evaluation of design changes in the memory controller and DRAM to meet the increasing research effort in improving the perfo... » read more

RowPress: Read-Disturb Phenomenon In DDR4 DRAM Chips
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" was published by researchers at ETH Zürich. Abstract: "Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and clo... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy