tag: rowhammer

Analyzing Rowhammer Vulnerability in Monolithic 3D IWO eDRAM for Edge (ASU, Georgia Tech)
By Technical Paper Link - 05 Jun, 2026 - Comments: 0

Researchers from Arizona State University and Georgia Institute of Technology published “Thermal- and Aging-Aware Rowhammer Vulnerability Analysis of Monolithically-Integrated IWO eDRAM for Edge Platforms”. "This work presents the first comprehensive temperature- and aging-aware vulnerability analysis of amorphous Indium Tungsten Oxide (IWO) embedded DRAM (eDRAM), a promising next-... » read more

GPU Rowhammer Attacks Beyond Data Corruption (U. of Toronto)
By Technical Paper Link - 13 Apr, 2026 - Comments: 0

A new technical paper, "GPUBreach: Privilege Escalation Attacks via GPU Rowhammer," was published by researchers at University of Toronto. Summary "GPUBreach shows that GPU Rowhammer attacks can move beyond data corruption to real privilege escalation. By corrupting GPU page tables, an unprivileged CUDA kernel can gain arbitrary GPU memory read/write, and then chain that capability into CPU... » read more

DRAM’s Whac‑A‑Mole Security Crisis
By Bryon Moyer - 09 Apr, 2026 - Comments: 0

Key takeaways: Rowhammer remains a DRAM security threat, while Rowpress has increasingly become a related threat. New commands issued by the memory controller can help manage refreshes, but they’re not a perfect solution. A smaller, vertical DRAM cell may eliminate the problem, but it’s years away. Rowhammer has been a persistent DRAM issue across several memory generati... » read more

The One Bit Problem That Can Break a System
By Ann Mutschler - 02 Apr, 2026 - Comments: 2

Key Takeaways: Bit flipping is no longer a rare reliability issue but a systemic risk driven by shrinking process nodes, higher clock speeds, lower voltages, and radiation exposure, leading to silent data corruption and potential system failure. The same mechanisms that cause accidental bit flips can be deliberately exploited through techniques such as clock, voltage, laser, and rowhamm... » read more

How SW and HW Vulnerabilities Can Complement LLM-Specific Algorithmic Attacks (UT Austin, Intel et al.)
By Technical Paper Link - 20 Mar, 2026 - Comments: 0

A new technical paper, "Cascade: Composing Software-Hardware Attack Gadgets for Adversarial Threat Amplification in Compound AI Systems," was published by the University of Texas, Austin, Intel Labs, Symmetry Systems, Microsoft and Georgia Tech. Abstract "Rapid progress in generative AI has given rise to Compound AI systems - pipelines comprised of multiple large language models (LLM), so... » read more

Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips," was published by ETH Zurich and Rutgers University. Abstract "State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read disturba... » read more

A Decade Of Architectural RowHammer Defense Solutions (Meta, SNU, UIUC)
By Technical Paper Link - 19 Nov, 2025 - Comments: 0

A new technical paper titled "SoK: Systematizing a Decade of Architectural RowHammer Defenses Through the Lens of Streaming Algorithms" was published by researchers at Meta, Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "A decade after its academic introduction, RowHammer (RH) remains a moving target that continues to challenge both the industry and aca... » read more

Algorithms For Black-Box, Physical-to-DRAM Address-Mapping Recovery (Georgia Tech, CNRS, Et Al.)
By Technical Paper Link - 06 Oct, 2025 - Comments: 0

A new technical paper titled "Knock-Knock: Black-Box, Platform-Agnostic DRAM Address-Mapping Reverse Engineering" was published by researchers at Georgia Tech, ESILV, CentraleSupelec, Inria, CNRS, IRISA. Abstract "Modern Systems-on-Chip (SoCs) employ undocumented linear address-scrambling functions to obfuscate DRAM addressing, which complicates DRAM-aware performance optimizations and hind... » read more

Security Technical Paper Roundup: Sept. 30
By Linda Christensen - 30 Sep, 2025 - Comments: 0

A number of hardware security-related technical papers were presented at the August 2025 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, rowhammer, and more. Here are some highlights with associated links: [ta... » read more

The Evolution of DRAM
By Ed Sperling - 08 Sep, 2025 - Comments: 1

DRAM has been around since 1966, but today it's still the same basic 1T 1C bit cell architecture. Yet changes are coming as DRAM is called upon to store and retrieve more data faster. Steve Woo, distinguished inventor and fellow at Rambus, talks about how DRAM works, why there are different flavors, the impact of cooling new solutions in denser configurations, and ongoing issues involving the s... » read more

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