Chip Industry Technical Paper Roundup: August 15

Chiplet integration; RISC-V memory safety; chip industry workforce aid; power leakage attack; search tool for hybrid-device IMC architectures for DNNs; e-graph verification assistant; chiplet-based FHE accelerator; vertical 2D channels enabling fast Li-ion migration; Si-photonic neural networks.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
From Talent Shortage to Workforce Excellence in the CHIPS Act Era: Harnessing Industry 4.0 Paradigms for a Sustainable Future in Domestic Chip Production University of Florida Gainesville, ZEISS Microscopy, and US Partnership for Assured Electronics (USPAE)
RV-CURE: A RISC-V Capability Architecture for Full Memory Safety Georgia Tech and Arm Research
Floorplet: Performance-aware Floorplan Framework for Chiplet Integration Chinese University of Hong Kong and University of California Berkeley
Analysis of Optical Loss and Crosstalk Noise in MZI-based Coherent Photonic Neural Networks Colorado State University (Fort Collins), NVIDIA, and Arizona State University
Collide+Power: Leaking Inaccessible Data with Software-based Power Side Channels Graz University of Technology and CISPA Helmholtz Center for Information Security
HyDe: A Hybrid PCM/FeFET/SRAM Device-search for Optimizing Area and Energy-efficiencies in Analog IMC Platforms Yale University
Datapath Verification via Word-Level E-Graph Rewriting Intel Corporation and Imperial College London
REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption Graz University of Technology, Samsung Advanced Institute of Technology
Li iontronics in single-crystalline T-Nb2O5 thin films with vertical ionic transport channels Max Planck Institute of Microstructure Physics, University of Cambridge, University of Pennsylvania, Gumi Electronics and Information Technology Research Institute, Northwestern University, and ALBA Synchrotron Light Source

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