Chip Industry Technical Paper Roundup: August 15


New technical papers added to Semiconductor Engineering’s library this week. [table id=128 /] More Reading Technical Paper Library home » read more

Week In Review: Auto, Security, Pervasive Computing


Intel issued an advisory of a potential security vulnerability in some of its processors. The company recommends updating to the latest firmware version. NVIDIA unveiled its GH200 Grace Hopper platform, based on 144 Arm Neoverse cores and 282GB of HBM3e memory. Meanwhile, Chinese internet companies including Baidu, ByteDance, Tencent, and Alibaba ordered about $5 billion worth of A800 proces... » read more

A RISC-V Capability Architecture Orchestrating Compiler, Architecture, And System Designs For Full Memory Safety (Georgia Tech, Arm Research)


A technical paper titled “RV-CURE: A RISC-V Capability Architecture for Full Memory Safety” was published by researchers at Georgia Institute of Technology and Arm Research. Abstract: "Despite decades of efforts to resolve, memory safety violations are still persistent and problematic in modern systems. Various defense mechanisms have been proposed, but their deployment in real systems re... » read more

Research Bits: Aug. 23


Algae-powered microprocessor Engineers from the University of Cambridge, Arm Research, Scottish Association for Marine Science, and Norwegian University of Science and Technology used a widespread species of blue-green algae to power an Arm Cortex M0+ microprocessor continuously for over a year. The algae, Synechocystis, is non-toxic and harvests energy from photosynthesis. The tiny electri... » read more

Technical Paper Round-Up: Aug 23


New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Every Walk’s A Hit: Making Page Walks Single-Access Cache Hits


As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB p... » read more

Research Bits: April 19


Processor power prediction Researchers from Duke University, Arm Research, and Texas A&M University developed an AI method for predicting the power consumption of a processor, returning results more than a trillion times per second while consuming very little power itself. “This is an intensively studied problem that has traditionally relied on extra circuitry to address,” said Zhiy... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences


Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

Week In Review: Design, Low Power


Siemens will acquire Avatar Integrated Systems. The company's place-and-route tools, which will become part of Mentor's Xcelerator portfolio, include a netlist-to-GDS full-function block-level physical implementation tool and a complete top-level prototyping, floor-planning and chip assembly tool. Based in Santa Clara, CA, Avatar was formed in 2017 from the acquired assets of ATopTech. ATopTech... » read more