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Every Walk’s A Hit: Making Page Walks Single-Access Cache Hits


As memory capacity has outstripped TLB coverage, large data applications suffer from frequent page table walks. We investigate two complementary techniques for addressing this cost: reducing the number of accesses required and reducing the latency of each access. The first approach is accomplished by opportunistically "flattening" the page table: merging two levels of traditional 4 KB p... » read more

Research Bits: April 19


Processor power prediction Researchers from Duke University, Arm Research, and Texas A&M University developed an AI method for predicting the power consumption of a processor, returning results more than a trillion times per second while consuming very little power itself. “This is an intensively studied problem that has traditionally relied on extra circuitry to address,” said Zhiy... » read more

Execution Dependence Extension (EDE): ISA Support For Eliminating Fences


Fence instructions are a coarse-grained mechanism to enforce the order of instruction execution in an out-of-order pipeline. They are an overkill for cases when only one instruction must wait for the completion of one other instruction. For example, this is the case when performing undo logging in Non-Volatile Memory (NVM) systems: while the update of a variable needs to wait until the correspo... » read more

Week In Review: Design, Low Power


Siemens will acquire Avatar Integrated Systems. The company's place-and-route tools, which will become part of Mentor's Xcelerator portfolio, include a netlist-to-GDS full-function block-level physical implementation tool and a complete top-level prototyping, floor-planning and chip assembly tool. Based in Santa Clara, CA, Avatar was formed in 2017 from the acquired assets of ATopTech. ATopTech... » read more