Week In Review: Design, Low Power

Mentor boosts place-and-route with Avatar acquisition; DDR5 published; EDA revenue up 3.5%.


Siemens will acquire Avatar Integrated Systems. The company’s place-and-route tools, which will become part of Mentor’s Xcelerator portfolio, include a netlist-to-GDS full-function block-level physical implementation tool and a complete top-level prototyping, floor-planning and chip assembly tool. Based in Santa Clara, CA, Avatar was formed in 2017 from the acquired assets of ATopTech. ATopTech, founded in 2004, had filed for bankruptcy after losing a copyright infringement lawsuit brought by Synopsys. “Avatar’s approach can lead to excellent correlation through all phases of place and route, with improved PPA results,” said Avatar CTO Ping San Tzeng. “As a part of Siemens, Avatar can further develop this approach, accelerate R&D, and grow market share by leveraging a much larger pool of resources.” The deal is expected to close in the second half of 2020. Terms were not disclosed.

Analog Devices will acquire Maxim Integrated in a deal worth about $21 billion, one of the largest acquisitions in recent years. The combination of the two companies is set to create an analog semiconductor powerhouse, boosting ADI’s number two ranking in analog IC sales for 2019. The all-stock transaction will result in current ADI stockholders owning ~69% of the combined company, while Maxim stockholders will own ~31%. The deal is expected to close in summer 2021.

Tools & IP
Synopsys debuted verification IP for DDR5 DRAM/DIMM, compliant with JESD79-5. The VIP uses a native SystemVerilog UVM architecture, is integrated with Synopsys’ Verdi Protocol and Performance Analyzer, and includes built-in coverage and verification plans.

Mentor and Samsung Foundry teamed up to develop a design solution kit (SF-DSK) that connects Samsung’s efuse to Tessent MemoryBIST built-in self-repair software. The kit aims to help fab customers simplify testing, diagnosis and repair of embedded memory in advanced SoCs.

Flex Logix introduced EFLX eFPGA IP emulation models for use on the Cadence Palladium Z1 platform, enabling verification of SoCs, subsystems and IP blocks as well as system-level validation.

Ansys released the latest version of its engineering simulation software, Ansys 2020 R2. For automotive, 2020 R2 adds advanced LiDAR models, new sky model for enhanced daylight simulation, improved thermal modeling, and a New Car Assessment Program scenario kit for autonomous vehicle development. To boost 5G development, it improves phased array antenna analysis to simulate larger, more complex designs with scalable leveraging of HPC. Ansys also debuted Ansys Discovery, which combines interactive real-time simulation, high-fidelity solver technology, and direct modeling in a single tool.

Agnisys uncorked three new products: SLIP-G, SoC Enterprise, and IDS NextGen. Standard Library of IP Generators (SLIP-G) provides an interface for IP customization and configuration, and generates the IP RTL design, testbench models compliant with UVM, and programming sequences for GPIO, I2C, timer, and PIC. SoC Enterprise (SoC-E) automatically generates RTL aggregators, bridges, and multiplexors for IP integration into an SoC. IDS NextGen (IDS-NG) is a specialized IDE for large IP blocks and SoCs and provides a common front end for multiple tools.

Axiomise launched a new RISC-V formal verification app, formalISA. The GUI-enabled app provides coverage analysis and end-to-end verification of architectural checks of the RISC-V ISA against the implementation without the need to write tests. It is compatible with leading commercial formal verification tools.

Arm Flexible Access for Research is now available. The program provides free access to Arm IP for academic research use and includes access to full RTL for a range of Arm Cortex-A, Cortex-R and Cortex-M CPUs, Mali GPUs, tools, and subsystems.

JEDEC published the DDR5 standard, JESD79-5. DDR5 supports double the bandwidth as compared to its predecessor and is expected to be launched at 4.8 Gbps (50% higher than DDR4’s end of life speed of 3.2 Gbps). New in the standard is a doubling of burst-length to BL16 and bank-count to 32 from 16 to  enable scaling memory performance without degrading channel efficiency at higher speeds. The DDR5 DIMM has two 40-bit fully independent sub-channels on the same module for efficiency and improved reliability.

SATA-IO published the SATA Revision 3.5 specification. Focused on performance improvements and integration with other I/O standards, key updates to the specification include Device Transmit Emphasis for Gen 3 PHY, the ability to specify the processing relationships among queued commands, and latency reduction by allowing the host to define quality of service categories.

Arm Research announced it is working on DARPA’s Automatic Implementation of Secure Silicon (AISS) program. There are three components Arm Research is participating in: development of a secure extensible reference platform, a secure verification and implementation reference flow, and a fully attested device management workflow supported by an associated design and provisioning infrastructure.

Tenstorrent utilized Synopsys’ DesignWare PCIe 4.0 Controller and PHY, ARC HS48 Processor, and LPDDR4 Controller IP in its Grayskull AI processor SoC, which achieved first-pass silicon success. In choosing the IP, Tenstorrent cited speed of integration, support, and IP quality.

VITEC licensed Codasip’s Bk5 RISC-V-based core for its video and audio stream handling solutions. The multi-use license, initially for an extended Bk5 64-bit configuration to be used in a video transcoder, allows VITEC to use any Bk5 32 or 64-bit configuration in future designs and other arising use cases. VITEC cited the customizability of the core and its ability to match diverse market segments.

EDA industry revenue for the first quarter of 2020 was $2.698 billion, increasing 3.5% compared to the same quarter last year, according to the ESD Alliance’s Market Statistics Service. The four-quarter moving average increased 5.2%. The two strongest categories were IP, which with $985.6 million saw a 12.5% increase from a year ago and 9.6% increase on the four-quarter moving average, and PCB and MCM, which had revenue of $250.9 million, an increase of 12% over Q1 2019 and 14.1% on the moving average. EMEA was the region with the largest revenue growth, increasing 13.4% (11.1% four-quarter moving average) to $392.3 million.

Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead?

DAC will be a virtual event this year. It will still take place July 19 – 23, 2020. Watch what’s new in this year’s content and focus. Keynotes for the event will cover a system look at semiconductor technology, the RISC-V revolution, wafer-scale deep learning accelerators, and looking ahead to 6G.

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